forked from Github_Repos/cvw
97 lines
3.8 KiB
Systemverilog
97 lines
3.8 KiB
Systemverilog
///////////////////////////////////////////
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// 1 port sram.
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//
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// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by ross1728@gmail.com)
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// Created: 04 April 2023
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//
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// Purpose: ram1p1wre, but without byte-enable. Used for icache data.
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// Be careful using this module, since coverage is turned off for (ce & we).
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// In read-only caches, we never get (we=1, ce=0), so this waiver is needed.
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//
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// Documentation:
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
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`include "wally-config.vh"
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module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
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input logic clk,
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input logic ce,
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input logic [$clog2(DEPTH)-1:0] addr,
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input logic [WIDTH-1:0] din,
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input logic we,
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output logic [WIDTH-1:0] dout
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);
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logic [WIDTH-1:0] RAM[DEPTH-1:0];
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// ***************************************************************************
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// TRUE SRAM macro
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// ***************************************************************************
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if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
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// 64 x 128-bit SRAM
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ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
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.A(addr), .D(din),
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.BWEB('0), .Q(dout));
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end else if ((`USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag
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// 64 x 44-bit SRAM
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ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
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.A(addr), .D(din),
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.BWEB('0), .Q(dout));
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end else if ((`USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag
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// 64 x 22-bit SRAM
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ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
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.A(addr), .D(din),
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.BWEB('0), .Q(dout));
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// ***************************************************************************
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// READ first SRAM model
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// ***************************************************************************
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end else begin: ram
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// *** Vivado is not implementing this as block ram for some reason.
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// The version with byte write enables it correctly infers block ram.
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integer i;
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// Read
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logic [$clog2(DEPTH)-1:0] addrd;
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flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
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assign dout = RAM[addrd];
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/* // Read
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always_ff @(posedge clk)
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if(ce) dout <= #1 mem[addr]; */
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// Write divided into part for bytes and part for extra msbs
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// Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
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// Therefore these always blocks use the older always @(posedge clk)
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always @(posedge clk)
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// coverage off
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// ce only goes low when cachefsm is in READY state and Flush is asserted.
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// for read-only caches, we only goes high in the STATE_WRITE_LINE cachefsm state.
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// so we can never get we=1, ce=0 for I$.
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if (ce & we)
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// coverage on
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RAM[addr] <= #1 din;
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end
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endmodule
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