forked from Github_Repos/cvw
123 lines
2.9 KiB
Systemverilog
123 lines
2.9 KiB
Systemverilog
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`include "wally-config.vh"
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`define DIVLEN ((`NF<`XLEN) ? `XLEN : `NF)
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///////////
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// clock //
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///////////
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module clock(clk);
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output clk;
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// Internal clk signal
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logic clk;
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endmodule
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//////////
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// testbench //
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//////////
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module testbenchradix4;
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logic clk;
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logic req;
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logic DivDone;
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logic [63:0] a, b;
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logic [51:0] afrac, bfrac;
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logic [10:0] aExp, bExp;
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logic asign, bsign;
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logic [51:0] r, rOTFC;
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logic [`DIVLEN-1:0] Quot, QuotOTFC;
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logic [54:0] rp, rm; // positive quotient digits
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// Test parameters
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parameter MEM_SIZE = 40000;
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parameter MEM_WIDTH = 64+64+64;
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`define memr 63:0
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`define memb 127:64
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`define mema 191:128
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// Test logicisters
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logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
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logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a
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// bit field of an array
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logic [63:0] correctr, nextr, diffn, diffp;
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logic [10:0] DivExp;
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logic DivSgn;
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integer testnum, errors;
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// Divider
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srtradix4 srtradix4(.clk, .DivStart(req),
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.XExpE(aExp), .YExpE(bExp), .DivExp,
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.XSgnE(asign), .YSgnE(bsign), .DivSgn,
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.XFrac(afrac), .YFrac(bfrac),
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.SrcA('0), .SrcB('0),
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.W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), .DivDone,
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.Quot, .Rem());
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// Counter
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initial
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forever
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begin
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clk = 1; #17;
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clk = 0; #17;
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end
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// Read test vectors from disk
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initial
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begin
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testnum = 0;
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errors = 0;
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$readmemh ("testvectors", Tests);
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Vec = Tests[testnum];
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a = Vec[`mema];
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{asign, aExp, afrac} = a;
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b = Vec[`memb];
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{bsign, bExp, bfrac} = b;
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nextr = Vec[`memr];
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r = Quot[`DIVLEN-1:`DIVLEN - 52];
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req <= 1;
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end
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// Apply directed test vectors read from file.
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always @(posedge clk)
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begin
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r = Quot[`DIVLEN-1:`DIVLEN - 52];
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if (DivDone) begin
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req <= 1;
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diffp = correctr[51:0] - r;
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diffn = r - correctr[51:0];
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if ((DivSgn !== correctr[63]) | (DivExp !== correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
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begin
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errors = errors+1;
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$display("result was %h_%h, should be %h %h %h\n", DivExp, r, correctr, diffn, diffp);
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$display("failed\n");
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$stop;
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end
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if (afrac === 52'hxxxxxxxxxxxxx)
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begin
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$display("%d Tests completed successfully", testnum);
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$stop;
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end
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end
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if (req)
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begin
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req <= 0;
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correctr = nextr;
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testnum = testnum+1;
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Vec = Tests[testnum];
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$display("a = %h b = %h",a,b);
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a = Vec[`mema];
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{asign, aExp, afrac} = a;
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b = Vec[`memb];
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{bsign, bExp, bfrac} = b;
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nextr = Vec[`memr];
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end
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end
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endmodule
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