forked from Github_Repos/cvw
29743c5e9e
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly. Second the bidir buffer for the sd card was connected backwards.
458 lines
14 KiB
Verilog
458 lines
14 KiB
Verilog
///////////////////////////////////////////
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// fpgaTop.sv
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//
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// Written: ross1728@gmail.com November 17, 2021
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// Modified:
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//
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// Purpose: This is a top level for the fpga's implementation of wally.
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// Instantiates wallysoc, ddr4, abh lite to axi converters, pll, etc
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module fpgaTop
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(input default_250mhz_clk1_0_n,
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input default_250mhz_clk1_0_p,
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input reset,
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input south_rst,
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input [3:0] GPI,
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output [4:0] GPO,
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input UARTSin,
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output UARTSout,
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input [3:0] SDCDat,
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output SDCCLK,
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inout SDCCmd,
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output calib,
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output cpu_reset,
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output ahblite_resetn,
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output [16 : 0] c0_ddr4_adr,
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output [1 : 0] c0_ddr4_ba,
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output [0 : 0] c0_ddr4_cke,
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output [0 : 0] c0_ddr4_cs_n,
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inout [7 : 0] c0_ddr4_dm_dbi_n,
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inout [63 : 0] c0_ddr4_dq,
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inout [7 : 0] c0_ddr4_dqs_c,
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inout [7 : 0] c0_ddr4_dqs_t,
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output [0 : 0] c0_ddr4_odt,
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output [0 : 0] c0_ddr4_bg,
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output c0_ddr4_reset_n,
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output c0_ddr4_act_n,
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output [0 : 0] c0_ddr4_ck_c,
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output [0 : 0] c0_ddr4_ck_t
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);
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wire CPUCLK;
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wire c0_ddr4_ui_clk_sync_rst;
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wire bus_struct_reset;
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wire peripheral_reset;
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wire interconnect_aresetn;
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wire peripheral_aresetn;
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wire mb_reset;
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wire [`AHBW-1:0] HRDATAEXT;
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wire HREADYEXT;
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wire HRESPEXT;
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wire HSELEXT;
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wire HCLKOpen;
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wire HRESETnOpen;
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wire [31:0] HADDR;
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wire [`AHBW-1:0] HWDATA;
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wire HWRITE;
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wire [2:0] HSIZE;
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wire [2:0] HBURST;
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wire [3:0] HPROT;
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wire [1:0] HTRANS;
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wire HMASTLOCK;
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wire HREADY;
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wire [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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wire SDCCmdIn;
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wire SDCCmdOE;
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wire SDCCmdOut;
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wire [3:0] m_axi_awid;
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wire [7:0] m_axi_awlen;
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wire [2:0] m_axi_awsize;
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wire [1:0] m_axi_awburst;
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wire [3:0] m_axi_awcache;
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wire [31:0] m_axi_awaddr;
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wire [2:0] m_axi_awprot;
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wire m_axi_awvalid;
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wire m_axi_awready;
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wire m_axi_awlock;
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wire [63:0] m_axi_wdata;
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wire [7:0] m_axi_wstrb;
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wire m_axi_wlast;
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wire m_axi_wvalid;
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wire m_axi_wready;
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wire [3:0] m_axi_bid;
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wire [1:0] m_axi_bresp;
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wire m_axi_bvalid;
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wire m_axi_bready;
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wire [3:0] m_axi_arid;
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wire [7:0] m_axi_arlen;
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wire [2:0] m_axi_arsize;
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wire [1:0] m_axi_arburst;
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wire [2:0] m_axi_arprot;
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wire [3:0] m_axi_arcache;
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wire m_axi_arvalid;
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wire [31:0] m_axi_araddr;
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wire m_axi_arlock;
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wire m_axi_arready;
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wire [3:0] m_axi_rid;
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wire [63:0] m_axi_rdata;
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wire [1:0] m_axi_rresp;
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wire m_axi_rvalid;
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wire m_axi_rlast;
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wire m_axi_rready;
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wire [3:0] BUS_axi_arregion;
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wire [3:0] BUS_axi_arqos;
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wire [3:0] BUS_axi_awregion;
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wire [3:0] BUS_axi_awqos;
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wire [3:0] BUS_axi_awid;
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wire [7:0] BUS_axi_awlen;
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wire [2:0] BUS_axi_awsize;
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wire [1:0] BUS_axi_awburst;
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wire [3:0] BUS_axi_awcache;
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wire [30:0] BUS_axi_awaddr;
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wire [2:0] BUS_axi_awprot;
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wire BUS_axi_awvalid;
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wire BUS_axi_awready;
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wire BUS_axi_awlock;
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wire [63:0] BUS_axi_wdata;
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wire [7:0] BUS_axi_wstrb;
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wire BUS_axi_wlast;
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wire BUS_axi_wvalid;
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wire BUS_axi_wready;
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wire [3:0] BUS_axi_bid;
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wire [1:0] BUS_axi_bresp;
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wire BUS_axi_bvalid;
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wire BUS_axi_bready;
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wire [3:0] BUS_axi_arid;
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wire [7:0] BUS_axi_arlen;
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wire [2:0] BUS_axi_arsize;
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wire [1:0] BUS_axi_arburst;
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wire [2:0] BUS_axi_arprot;
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wire [3:0] BUS_axi_arcache;
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wire BUS_axi_arvalid;
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wire [30:0] BUS_axi_araddr;
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wire BUS_axi_arlock;
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wire BUS_axi_arready;
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wire [3:0] BUS_axi_rid;
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wire [63:0] BUS_axi_rdata;
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wire [1:0] BUS_axi_rresp;
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wire BUS_axi_rvalid;
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wire BUS_axi_rlast;
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wire BUS_axi_rready;
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wire BUSCLK;
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wire c0_init_calib_complete;
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wire dbg_clk;
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wire [511 : 0] dbg_bus;
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wire CLK208;
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assign GPIOPinsIn = {28'b0, GPI};
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assign GPO = GPIOPinsOut[4:0];
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assign ahblite_resetn = peripheral_aresetn;
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assign cpu_reset = bus_struct_reset;
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assign calib = c0_init_calib_complete;
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// SD Card Tristate
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IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low
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.I(SDCCmdOut),
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.O(SDCCmdIn),
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.IO(SDCCmd));
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// reset controller XILINX IP
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xlnx_proc_sys_reset xlnx_proc_sys_reset_0
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(.slowest_sync_clk(CPUCLK),
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.ext_reset_in(c0_ddr4_ui_clk_sync_rst),
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.aux_reset_in(south_rst),
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.mb_debug_sys_rst(1'b0),
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.dcm_locked(c0_init_calib_complete),
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.mb_reset(mb_reset), //open
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.bus_struct_reset(bus_struct_reset),
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.peripheral_reset(peripheral_reset), //open
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.interconnect_aresetn(interconnect_aresetn), //open
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.peripheral_aresetn(peripheral_aresetn));
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// wally
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wallypipelinedsoc wallypipelinedsoc
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(.clk(CPUCLK),
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.reset_ext(bus_struct_reset),
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// bus interface
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.HRDATAEXT(HRDATAEXT),
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.HREADYEXT(HREADYEXT),
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.HRESPEXT(HRESPEXT),
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.HSELEXT(HSELEXT),
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.HCLK(HCLKOpen), // open
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.HRESETn(HRESETnOpen), // open
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.HADDR(HADDR),
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.HWDATA(HWDATA),
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.HWRITE(HWRITE),
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.HSIZE(HSIZE),
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.HBURST(HBURST),
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.HPROT(HPROT),
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.HTRANS(HTRANS),
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.HMASTLOCK(HMASTLOCK),
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.HREADY(HREADY),
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// GPIO
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.GPIOPinsIn(GPIOPinsIn),
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.GPIOPinsOut(GPIOPinsOut),
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.GPIOPinsEn(GPIOPinsEn),
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// UART
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.UARTSin(UARTSin),
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.UARTSout(UARTSout),
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// SD Card
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.SDCDatIn(SDCDat),
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.SDCCmdIn(SDCCmdIn),
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.SDCCmdOut(SDCCmdOut),
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.SDCCmdOE(SDCCmdOE),
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.SDCCLK(SDCCLK));
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// ahb lite to axi bridge
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xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0
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(.s_ahb_hclk(CPUCLK),
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.s_ahb_hresetn(peripheral_aresetn),
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.s_ahb_hsel(HSELEXT),
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.s_ahb_haddr(HADDR),
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.s_ahb_hprot(HPROT),
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.s_ahb_htrans(HTRANS),
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.s_ahb_hsize(HSIZE),
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.s_ahb_hwrite(HWRITE),
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.s_ahb_hburst(HBURST),
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.s_ahb_hwdata(HWDATA),
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.s_ahb_hready_out(HREADYEXT),
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.s_ahb_hready_in(HREADY),
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.s_ahb_hrdata(HRDATAEXT),
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.s_ahb_hresp(HRESPEXT),
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.m_axi_awid(m_axi_awid),
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.m_axi_awlen(m_axi_awlen),
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.m_axi_awsize(m_axi_awsize),
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.m_axi_awburst(m_axi_awburst),
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.m_axi_awcache(m_axi_awcache),
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.m_axi_awaddr(m_axi_awaddr),
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.m_axi_awprot(m_axi_awprot),
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.m_axi_awvalid(m_axi_awvalid),
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.m_axi_awready(m_axi_awready),
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.m_axi_awlock(m_axi_awlock),
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.m_axi_wdata(m_axi_wdata),
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.m_axi_wstrb(m_axi_wstrb),
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.m_axi_wlast(m_axi_wlast),
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.m_axi_wvalid(m_axi_wvalid),
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.m_axi_wready(m_axi_wready),
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.m_axi_bid(m_axi_bid),
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.m_axi_bresp(m_axi_bresp),
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.m_axi_bvalid(m_axi_bvalid),
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.m_axi_bready(m_axi_bready),
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.m_axi_arid(m_axi_arid),
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.m_axi_arlen(m_axi_arlen),
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.m_axi_arsize(m_axi_arsize),
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.m_axi_arburst(m_axi_arburst),
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.m_axi_arprot(m_axi_arprot),
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.m_axi_arcache(m_axi_arcache),
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.m_axi_arvalid(m_axi_arvalid),
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.m_axi_araddr(m_axi_araddr),
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.m_axi_arlock(m_axi_arlock),
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.m_axi_arready(m_axi_arready),
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.m_axi_rid(m_axi_rid),
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.m_axi_rdata(m_axi_rdata),
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.m_axi_rresp(m_axi_rresp),
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.m_axi_rvalid(m_axi_rvalid),
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.m_axi_rlast(m_axi_rlast),
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.m_axi_rready(m_axi_rready));
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xlnx_axi_clock_converter xlnx_axi_clock_converter_0
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(.s_axi_aclk(CPUCLK),
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.s_axi_aresetn(peripheral_aresetn),
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.s_axi_awid(m_axi_awid),
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.s_axi_awlen(m_axi_awlen),
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.s_axi_awsize(m_axi_awsize),
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.s_axi_awburst(m_axi_awburst),
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.s_axi_awcache(m_axi_awcache),
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.s_axi_awaddr(m_axi_awaddr[30:0]),
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.s_axi_awprot(m_axi_awprot),
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.s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs
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.s_axi_awqos(4'b0), // this could be a bug. bridge does not have these outputs
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.s_axi_awvalid(m_axi_awvalid),
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.s_axi_awready(m_axi_awready),
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.s_axi_awlock(m_axi_awlock),
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.s_axi_wdata(m_axi_wdata),
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.s_axi_wstrb(m_axi_wstrb),
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.s_axi_wlast(m_axi_wlast),
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.s_axi_wvalid(m_axi_wvalid),
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.s_axi_wready(m_axi_wready),
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.s_axi_bid(m_axi_bid),
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.s_axi_bresp(m_axi_bresp),
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.s_axi_bvalid(m_axi_bvalid),
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.s_axi_bready(m_axi_bready),
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.s_axi_arid(m_axi_arid),
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.s_axi_arlen(m_axi_arlen),
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.s_axi_arsize(m_axi_arsize),
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.s_axi_arburst(m_axi_arburst),
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.s_axi_arprot(m_axi_arprot),
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.s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs
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.s_axi_arqos(4'b0), // this could be a bug. bridge does not have these outputs
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.s_axi_arcache(m_axi_arcache),
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.s_axi_arvalid(m_axi_arvalid),
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.s_axi_araddr(m_axi_araddr[30:0]),
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.s_axi_arlock(m_axi_arlock),
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.s_axi_arready(m_axi_arready),
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.s_axi_rid(m_axi_rid),
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.s_axi_rdata(m_axi_rdata),
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.s_axi_rresp(m_axi_rresp),
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.s_axi_rvalid(m_axi_rvalid),
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.s_axi_rlast(m_axi_rlast),
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.s_axi_rready(m_axi_rready),
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.m_axi_aclk(BUSCLK),
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.m_axi_aresetn(~reset),
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.m_axi_awid(BUS_axi_awid),
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.m_axi_awlen(BUS_axi_awlen),
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.m_axi_awsize(BUS_axi_awsize),
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.m_axi_awburst(BUS_axi_awburst),
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.m_axi_awcache(BUS_axi_awcache),
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.m_axi_awaddr(BUS_axi_awaddr),
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.m_axi_awprot(BUS_axi_awprot),
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.m_axi_awregion(BUS_axi_awregion),
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.m_axi_awqos(BUS_axi_awqos),
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.m_axi_awvalid(BUS_axi_awvalid),
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.m_axi_awready(BUS_axi_awready),
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.m_axi_awlock(BUS_axi_awlock),
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.m_axi_wdata(BUS_axi_wdata),
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.m_axi_wstrb(BUS_axi_wstrb),
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.m_axi_wlast(BUS_axi_wlast),
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.m_axi_wvalid(BUS_axi_wvalid),
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.m_axi_wready(BUS_axi_wready),
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.m_axi_bid(BUS_axi_bid),
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.m_axi_bresp(BUS_axi_bresp),
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.m_axi_bvalid(BUS_axi_bvalid),
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.m_axi_bready(BUS_axi_bready),
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.m_axi_arid(BUS_axi_arid),
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.m_axi_arlen(BUS_axi_arlen),
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.m_axi_arsize(BUS_axi_arsize),
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.m_axi_arburst(BUS_axi_arburst),
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.m_axi_arprot(BUS_axi_arprot),
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.m_axi_arregion(BUS_axi_arregion),
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.m_axi_arqos(BUS_axi_arqos),
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.m_axi_arcache(BUS_axi_arcache),
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.m_axi_arvalid(BUS_axi_arvalid),
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.m_axi_araddr(BUS_axi_araddr),
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.m_axi_arlock(BUS_axi_arlock),
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.m_axi_arready(BUS_axi_arready),
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.m_axi_rid(BUS_axi_rid),
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.m_axi_rdata(BUS_axi_rdata),
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.m_axi_rresp(BUS_axi_rresp),
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.m_axi_rvalid(BUS_axi_rvalid),
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.m_axi_rlast(BUS_axi_rlast),
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.m_axi_rready(BUS_axi_rready));
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xlnx_ddr4 xlnx_ddr4_c0
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(.c0_init_calib_complete(c0_init_calib_complete),
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.dbg_clk(dbg_clk), // open
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.c0_sys_clk_p(default_250mhz_clk1_0_p),
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.c0_sys_clk_n(default_250mhz_clk1_0_n),
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.sys_rst(reset),
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.dbg_bus(dbg_bus), // open
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// ddr4 I/O
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.c0_ddr4_adr(c0_ddr4_adr),
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.c0_ddr4_ba(c0_ddr4_ba),
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.c0_ddr4_cke(c0_ddr4_cke),
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.c0_ddr4_cs_n(c0_ddr4_cs_n),
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.c0_ddr4_dm_dbi_n(c0_ddr4_dm_dbi_n),
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.c0_ddr4_dq(c0_ddr4_dq),
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.c0_ddr4_dqs_c(c0_ddr4_dqs_c),
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.c0_ddr4_dqs_t(c0_ddr4_dqs_t),
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.c0_ddr4_odt(c0_ddr4_odt),
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.c0_ddr4_bg(c0_ddr4_bg),
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.c0_ddr4_reset_n(c0_ddr4_reset_n),
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.c0_ddr4_act_n(c0_ddr4_act_n),
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.c0_ddr4_ck_c(c0_ddr4_ck_c),
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.c0_ddr4_ck_t(c0_ddr4_ck_t),
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.c0_ddr4_ui_clk(BUSCLK),
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.c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst),
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.c0_ddr4_aresetn(~reset),
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// axi
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.c0_ddr4_s_axi_awid(BUS_axi_awid),
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.c0_ddr4_s_axi_awaddr(BUS_axi_awaddr[30:0]),
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.c0_ddr4_s_axi_awlen(BUS_axi_awlen),
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.c0_ddr4_s_axi_awsize(BUS_axi_awsize),
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.c0_ddr4_s_axi_awburst(BUS_axi_awburst),
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.c0_ddr4_s_axi_awlock(BUS_axi_awlock),
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.c0_ddr4_s_axi_awcache(BUS_axi_awcache),
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.c0_ddr4_s_axi_awprot(BUS_axi_awprot),
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.c0_ddr4_s_axi_awqos(BUS_axi_awqos),
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.c0_ddr4_s_axi_awvalid(BUS_axi_awvalid),
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.c0_ddr4_s_axi_awready(BUS_axi_awready),
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.c0_ddr4_s_axi_wdata(BUS_axi_wdata),
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.c0_ddr4_s_axi_wstrb(BUS_axi_wstrb),
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.c0_ddr4_s_axi_wlast(BUS_axi_wlast),
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|
.c0_ddr4_s_axi_wvalid(BUS_axi_wvalid),
|
|
.c0_ddr4_s_axi_wready(BUS_axi_wready),
|
|
.c0_ddr4_s_axi_bready(BUS_axi_bready),
|
|
.c0_ddr4_s_axi_bid(BUS_axi_bid),
|
|
.c0_ddr4_s_axi_bresp(BUS_axi_bresp),
|
|
.c0_ddr4_s_axi_bvalid(BUS_axi_bvalid),
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|
.c0_ddr4_s_axi_arid(BUS_axi_arid),
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|
.c0_ddr4_s_axi_araddr(BUS_axi_araddr[30:0]),
|
|
.c0_ddr4_s_axi_arlen(BUS_axi_arlen),
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|
.c0_ddr4_s_axi_arsize(BUS_axi_arsize),
|
|
.c0_ddr4_s_axi_arburst(BUS_axi_arburst),
|
|
.c0_ddr4_s_axi_arlock(BUS_axi_arlock),
|
|
.c0_ddr4_s_axi_arcache(BUS_axi_arcache),
|
|
.c0_ddr4_s_axi_arprot(BUS_axi_arprot),
|
|
.c0_ddr4_s_axi_arqos(BUS_axi_arqos),
|
|
.c0_ddr4_s_axi_arvalid(BUS_axi_arvalid),
|
|
.c0_ddr4_s_axi_arready(BUS_axi_arready),
|
|
.c0_ddr4_s_axi_rready(BUS_axi_rready),
|
|
.c0_ddr4_s_axi_rlast(BUS_axi_rlast),
|
|
.c0_ddr4_s_axi_rvalid(BUS_axi_rvalid),
|
|
.c0_ddr4_s_axi_rresp(BUS_axi_rresp),
|
|
.c0_ddr4_s_axi_rid(BUS_axi_rid),
|
|
.c0_ddr4_s_axi_rdata(BUS_axi_rdata),
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|
|
|
.addn_ui_clkout1(CPUCLK),
|
|
.addn_ui_clkout2(CLK208));
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endmodule
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