forked from Github_Repos/cvw
50 lines
1.3 KiB
Plaintext
50 lines
1.3 KiB
Plaintext
Code Improvements
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David_Harris@hmc.edu 15 Nov 2021
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Remove depricated N-Mode stuff, including sd in privileged.sv
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Look at version 13? of privileged spec. What should we add?
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Reduce size of repo
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Timing optimization (Kip, Shreya)
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Use ForwardSrcA instead of SrcA for mdu / fpu
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Look at TLB -> PMP -> Access Fault -> Trap
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may be able to precompute
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Try flattening, see speedup
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Take out Mul synthesis modes
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RISCV-Arch-tests
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Port MMU tests
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FPU
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spec difference on signaling/quiet NAN propagation
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SRT Div/Sqrt (Katherine, maybe Udeema)
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Get riscv-arch-tests running (James, Katherine)
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Get testfloat all passing
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Katherine's FPU optimization
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Linux Boot
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Ben, Skyler
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FPGA Boot Linux (Ross)
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IFU/LSU
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Block diagrams, code cleanup
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Burst mode transfers to speed up IPC
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Implications of no byte enables on subword write - do stores take extra cycle, should this be avoided?
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28 nm Implementation
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Install processor
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Memory macros
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Synthesis & PNR
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Timing review
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Benchmarking
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Flow
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Kevin Kim has a makefile to check out and build all the pieces. Make sure this is running; change Repo README to use his makefile
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Code cleanup
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.* fixes by thanksgiving
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Rename top-level modules to abbreviations
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Rename muldiv to mdu
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Get rid of DESIGN_COMPILER flag and redundant multiplier |