forked from Github_Repos/cvw
151 lines
2.6 KiB
ArmAsm
151 lines
2.6 KiB
ArmAsm
// -----------
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// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
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// version : 0.5.1
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// timestamp : Wed Aug 4 06:39:00 2021 GMT
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// usage : riscv_ctg \
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// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
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// --base-isa rv32e \
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// --randomize
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// -----------
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//
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// -----------
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// Copyright (c) 2020. RISC-V International. All rights reserved.
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the c.jr instruction of the RISC-V C extension for the cjr covergroup.
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//
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV32EC")
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjr)
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RVTEST_SIGBASE( x1,signature_x1_1)
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inst_0:
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// rs1==x6,
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// opcode: c.jr; op1:x6
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TEST_CJR_OP(x7, x6, x1, 0)
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inst_1:
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// rs1==x15,
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// opcode: c.jr; op1:x15
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TEST_CJR_OP(x7, x15, x1, 4)
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inst_2:
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// rs1==x14,
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// opcode: c.jr; op1:x14
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TEST_CJR_OP(x7, x14, x1, 8)
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inst_3:
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// rs1==x13,
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// opcode: c.jr; op1:x13
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TEST_CJR_OP(x7, x13, x1, 12)
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inst_4:
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// rs1==x3,
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// opcode: c.jr; op1:x3
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TEST_CJR_OP(x7, x3, x1, 16)
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inst_5:
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// rs1==x8,
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// opcode: c.jr; op1:x8
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TEST_CJR_OP(x7, x8, x1, 20)
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inst_6:
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// rs1==x2,
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// opcode: c.jr; op1:x2
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TEST_CJR_OP(x7, x2, x1, 24)
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inst_7:
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// rs1==x4,
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// opcode: c.jr; op1:x4
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TEST_CJR_OP(x7, x4, x1, 28)
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inst_8:
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// rs1==x12,
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// opcode: c.jr; op1:x12
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TEST_CJR_OP(x7, x12, x1, 32)
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inst_9:
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// rs1==x5,
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// opcode: c.jr; op1:x5
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TEST_CJR_OP(x7, x5, x1, 36)
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inst_10:
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// rs1==x7,
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// opcode: c.jr; op1:x7
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TEST_CJR_OP(x3, x7, x1, 40)
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RVTEST_SIGBASE( x2,signature_x2_0)
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inst_11:
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// rs1==x9,
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// opcode: c.jr; op1:x9
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TEST_CJR_OP(x3, x9, x2, 0)
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inst_12:
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// rs1==x1,
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// opcode: c.jr; op1:x1
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TEST_CJR_OP(x3, x1, x2, 4)
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inst_13:
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// rs1==x11,
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// opcode: c.jr; op1:x11
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TEST_CJR_OP(x3, x11, x2, 8)
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inst_14:
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// rs1==x10,
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// opcode: c.jr; op1:x10
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TEST_CJR_OP(x3, x10, x2, 12)
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#endif
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RVTEST_CODE_END
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RVMODEL_HALT
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RVTEST_DATA_BEGIN
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.align 4
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rvtest_data:
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.word 0xbabecafe
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RVTEST_DATA_END
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RVMODEL_DATA_BEGIN
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signature_x1_0:
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.fill 0*(XLEN/32),4,0xdeadbeef
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signature_x1_1:
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.fill 11*(XLEN/32),4,0xdeadbeef
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signature_x2_0:
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.fill 4*(XLEN/32),4,0xdeadbeef
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#ifdef rvtest_mtrap_routine
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mtrap_sigptr:
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.fill 64*(XLEN/32),4,0xdeadbeef
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#endif
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#ifdef rvtest_gpr_save
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gpr_save:
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.fill 32*(XLEN/32),4,0xdeadbeef
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#endif
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RVMODEL_DATA_END
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