forked from Github_Repos/cvw
161 lines
3.2 KiB
ArmAsm
161 lines
3.2 KiB
ArmAsm
// -----------
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// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
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// version : 0.5.1
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// timestamp : Wed Aug 4 06:39:00 2021 GMT
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// usage : riscv_ctg \
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// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
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// --base-isa rv32e \
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// --randomize
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// -----------
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//
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// -----------
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// Copyright (c) 2020. RISC-V International. All rights reserved.
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the c.jal instruction of the RISC-V C extension for the cjal covergroup.
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//
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV32EC")
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*RV32.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjal)
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RVTEST_SIGBASE( x2,signature_x2_1)
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inst_0:
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// imm_val < 0,
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// opcode:c.jal; immval:0x10
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TEST_CJAL_OP(c.jal, x3, 0x10, 1b, x2, 0)
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inst_1:
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// imm_val == -1026,
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// opcode:c.jal; immval:0x402
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TEST_CJAL_OP(c.jal, x3, 0x402, 1b, x2, 4)
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inst_2:
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// imm_val == -514,
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// opcode:c.jal; immval:0x202
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TEST_CJAL_OP(c.jal, x3, 0x202, 1b, x2, 8)
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inst_3:
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// imm_val == -258,
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// opcode:c.jal; immval:0x102
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TEST_CJAL_OP(c.jal, x3, 0x102, 1b, x2, 12)
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inst_4:
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// imm_val == -130,
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// opcode:c.jal; immval:0x82
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TEST_CJAL_OP(c.jal, x3, 0x82, 1b, x2, 16)
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inst_5:
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// imm_val == -66,
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// opcode:c.jal; immval:0x42
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TEST_CJAL_OP(c.jal, x3, 0x42, 1b, x2, 20)
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inst_6:
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// imm_val == -34,
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// opcode:c.jal; immval:0x22
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TEST_CJAL_OP(c.jal, x3, 0x22, 1b, x2, 24)
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inst_7:
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// imm_val == -18,
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// opcode:c.jal; immval:0x12
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TEST_CJAL_OP(c.jal, x3, 0x12, 1b, x2, 28)
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inst_8:
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// imm_val == -10,
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// opcode:c.jal; immval:0xa
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TEST_CJAL_OP(c.jal, x3, 0xa, 1b, x2, 32)
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inst_9:
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// imm_val == 1024, imm_val > 0
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// opcode:c.jal; immval:0x400
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TEST_CJAL_OP(c.jal, x3, 0x400, 3f, x2, 36)
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inst_10:
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// imm_val == 512,
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// opcode:c.jal; immval:0x200
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TEST_CJAL_OP(c.jal, x3, 0x200, 3f, x2, 40)
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inst_11:
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// imm_val == 1364,
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// opcode:c.jal; immval:0x554
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TEST_CJAL_OP(c.jal, x3, 0x554, 3f, x2, 44)
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inst_12:
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// imm_val == -1366,
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// opcode:c.jal; immval:0x556
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TEST_CJAL_OP(c.jal, x3, 0x556, 1b, x2, 48)
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inst_13:
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// imm_val == 256,
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// opcode:c.jal; immval:0x100
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TEST_CJAL_OP(c.jal, x3, 0x100, 3f, x2, 52)
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inst_14:
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// imm_val == 128,
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// opcode:c.jal; immval:0x80
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TEST_CJAL_OP(c.jal, x3, 0x80, 3f, x2, 56)
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inst_15:
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// imm_val == 64,
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// opcode:c.jal; immval:0x40
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TEST_CJAL_OP(c.jal, x3, 0x40, 3f, x2, 60)
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inst_16:
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// imm_val == 32,
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// opcode:c.jal; immval:0x20
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TEST_CJAL_OP(c.jal, x3, 0x20, 3f, x2, 64)
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inst_17:
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// imm_val == 16,
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// opcode:c.jal; immval:0x10
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TEST_CJAL_OP(c.jal, x3, 0x10, 3f, x2, 68)
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#endif
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RVTEST_CODE_END
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RVMODEL_HALT
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RVTEST_DATA_BEGIN
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.align 4
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rvtest_data:
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.word 0xbabecafe
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RVTEST_DATA_END
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RVMODEL_DATA_BEGIN
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signature_x2_0:
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.fill 0*(XLEN/32),4,0xdeadbeef
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signature_x2_1:
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.fill 18*(XLEN/32),4,0xdeadbeef
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#ifdef rvtest_mtrap_routine
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mtrap_sigptr:
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.fill 64*(XLEN/32),4,0xdeadbeef
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#endif
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#ifdef rvtest_gpr_save
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gpr_save:
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.fill 32*(XLEN/32),4,0xdeadbeef
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#endif
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RVMODEL_DATA_END
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