cvw/wally-pipelined/regression
2021-09-25 19:05:07 -05:00
..
slack-notifier added slack notifier for long sims 2021-06-22 08:31:41 -04:00
wave-dos fixed bug where M mode was sensitive to S mode traps 2021-09-07 19:14:39 -04:00
linux-wave.do Fixed the amo on dcache miss cpu stall issue. 2021-09-17 22:15:03 -05:00
regression-wally.py Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-15 17:31:11 -04:00
run_sim.sh
sim-buildroot
sim-buildroot-batch
sim-busybear
sim-busybear-batch
sim-wally
sim-wally-arch-batch Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00
sim-wally-arch-batch-rv32ic Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 2021-09-13 12:40:40 -04:00
sim-wally-batch
sim-wally-batch-muldiv
sim-wally-batch-rv32ic
sim-wally-batch-rv32icfd Fixed lint warning 2021-07-14 21:24:48 -04:00
sim-wally-batch-rv64icfd
sim-wally-muldiv
sim-wally-rv32ic
sim-wally-rv32icfd Fixed lint warning 2021-07-14 21:24:48 -04:00
sim-wally-rv64icfd Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
udiv.c
wally-arch.do Cleaned up wally-arch test scripts 2021-09-13 00:02:32 -04:00
wally-buildroot-batch.do Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
wally-buildroot.do restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair 2021-09-04 19:45:04 -04:00
wally-busybear-batch.do Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
wally-busybear.do Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
wally-coremark_bare.do Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do. 2021-08-19 10:33:11 -05:00
wally-pipelined-batch-muldiv.do Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
wally-pipelined-batch-rv32icfd.do Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
wally-pipelined-batch-rv64icfd.do Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
wally-pipelined-batch.do Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
wally-pipelined-fpga.do Have program which checks for sdc init and issues read, but read done is 2021-09-24 15:53:38 -05:00
wally-pipelined-muldiv.do Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
wally-pipelined-ross.do Updated Dcache to fully support flush. This appears to work. 2021-09-17 10:25:21 -05:00
wally-pipelined-rv32icfd.do Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
wally-pipelined-rv64icfd.do Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
wally-pipelined.do Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
wally-privileged.do Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
wave-all.do Fixed busybear by restoring InstrValidW needed by testbench 2021-07-13 14:17:36 -04:00
wave.do Almost done writting driver for flash card reader. 2021-09-25 19:05:07 -05:00