Ross Thompson 49e75d579c Set associate icache working, but way 0 is never written.		2021-09-07 12:46:16 -05:00
..
cache	Set associate icache working, but way 0 is never written.	2021-09-07 12:46:16 -05:00
ebu	Additional cleanup of ahblite.	2021-08-25 22:53:20 -05:00
fpu	all conversions go through the execute stage result mux	2021-08-16 13:06:09 -04:00
generic	simplified or_rows generation and renamed oneHotDecoder to onehotdecoder	2021-08-25 06:46:41 -04:00
hazard	Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.	2021-08-23 15:46:17 -05:00
ieu	Moved the ReadDataW register into the datapath.	2021-07-22 14:52:03 -05:00
ifu	Fixed bugs I introduced to the icache.	2021-08-27 15:00:40 -05:00
lsu	Removed amo logic from ahblite. Removed many unused signals from ahblite.	2021-08-25 22:45:13 -05:00
mmu	partial dcache reorg.	2021-08-25 12:42:05 -05:00
muldiv	Fixed syntax errors in some floating point modules. This came up in	2021-08-15 16:48:49 -05:00
privileged	Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.	2021-08-23 15:46:17 -05:00
uncore	Modified invalid plic reads to return 0 rather than deadbeaf.	2021-08-11 16:56:22 -05:00
wally	Removed amo logic from ahblite. Removed many unused signals from ahblite.	2021-08-25 22:45:13 -05:00