forked from Github_Repos/cvw
109 lines
6.1 KiB
Systemverilog
109 lines
6.1 KiB
Systemverilog
///////////////////////////////////////////
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// hazard.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Determine stalls and flushes
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//
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// Documentation: RISC-V System on Chip Design Chapter 4, Figure 13.54
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module hazard(
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// Detect hazards
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(* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFenceM, RetM, TrapM,
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(* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
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(* mark_debug = "true" *) input logic LSUStallM, IFUStallF,
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(* mark_debug = "true" *) input logic FCvtIntStallD, FPUStallD,
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(* mark_debug = "true" *) input logic DivBusyE, FDivBusyE,
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(* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM,
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(* mark_debug = "true" *) input logic WFIStallM,
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// Stall & flush outputs
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(* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW,
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(* mark_debug = "true" *) output logic FlushD, FlushE, FlushM, FlushW
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);
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logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
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logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW;
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logic FlushDCause, FlushECause, FlushMCause, FlushWCause;
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// stalls and flushes
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// loads: stall for one cycle if the subsequent instruction depends on the load
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// branches and jumps: flush the next two instructions if the branch is taken in EXE
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// CSR Writes: stall all instructions after the CSR until it completes, except that PC must change when branch is resolved
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// this also applies to other privileged instructions such as M/S/URET, ECALL/EBREAK
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// Exceptions: flush entire pipeline
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// Ret instructions: occur in M stage. Might be possible to move earlier, but be careful about hazards
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// General stall and flush rules:
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// A stage must stall if the next stage is stalled
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// If any stages are stalled, the first stage that isn't stalled must flush.
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// Flush causes
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// Traps (TrapM) flush the entire pipeline.
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// However, breakpoint and ecall traps must finish the writeback stage (commit their results) because these instructions complete before trapping.
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// Trap returns (RetM) also flush the entire pipeline after the RetM (all stages except W) because all the subsequent instructions must be discarded.
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// Similarly, CSR writes and fences flush all subsequent instructions and refetch them in light of the new operating modes and cache/TLB contents
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// Branch misprediction is found in the Execute stage and must flush the next two instructions.
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// However, an active division operation resides in the Execute stage, and when the BP incorrectly mispredicts the divide as a taken branch, the divde must still complete
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assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPPredWrongE;
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assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPPredWrongE & ~(DivBusyE | FDivBusyE));
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assign FlushMCause = TrapM | RetM | CSRWriteFenceM;
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assign FlushWCause = TrapM & ~(BreakpointFaultM | EcallFaultM);
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// Stall causes
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// Most data depenency stalls are identified in the decode stage
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// Division stalls in the execute stage
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// Flushing any stage has priority over the corresponding stage stall.
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// Even if the register gave clear priority over enable, various FSMs still need to disable the stall, so it's best to gate the stall here with flush
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// The IFU and LSU stall the entire pipeline on a cache miss, bus access, or other long operation.
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// The IFU stalls the entire pipeline rather than just Fetch to avoid complications with instructions later in the pipeline causing Exceptions
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// A trap could be asserted at the start of a IFU/LSU stall, and should flush the memory operation
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assign StallFCause = '0;
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assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FPUStallD) & ~FlushDCause;
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assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause;
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assign StallMCause = WFIStallM & ~FlushMCause;
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// Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1.
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// assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause;
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// Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out.
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assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
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// Stall each stage for cause or if the next stage is stalled
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assign #1 StallF = StallFCause | StallD;
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assign #1 StallD = StallDCause | StallE;
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assign #1 StallE = StallECause | StallM;
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assign #1 StallM = StallMCause | StallW;
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assign #1 StallW = StallWCause;
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// detect the first stage that is not stalled
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assign FirstUnstalledD = ~StallD & StallF;
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assign FirstUnstalledE = ~StallE & StallD;
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assign FirstUnstalledM = ~StallM & StallE;
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assign FirstUnstalledW = ~StallW & StallM;
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// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
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assign #1 FlushD = FirstUnstalledD | FlushDCause;
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assign #1 FlushE = FirstUnstalledE | FlushECause;
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assign #1 FlushM = FirstUnstalledM | FlushMCause;
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assign #1 FlushW = FirstUnstalledW | FlushWCause;
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endmodule
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