David Harris 9c1b7e53e4 FPU divider working with execute stage stall		2022-12-02 11:11:53 -08:00
..
cache	Properly flush cacheLRU.	2022-12-01 17:32:58 -06:00
ebu	Moved all remaining bus logic from the LSU into ahbcacheinterface.	2022-11-11 14:30:32 -06:00
fpu	FPU divider working with execute stage stall	2022-12-02 11:11:53 -08:00
generic	Intermediate commit. Replaced flip flop dirty bit array with sram.	2022-11-30 00:08:31 -06:00
hazard	FPU divider working with execute stage stall	2022-12-02 11:11:53 -08:00
ieu	Eliminated store after store stall when no cache; simplified divshiftcalc logic.	2022-09-21 13:02:34 -07:00
ifu	I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.	2022-11-16 15:38:37 -06:00
lsu	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00
mmu	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00
muldiv	code cleanup	2022-12-01 08:15:48 -08:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00
uncore	Fixed the uart transmit fifo overrun bug.	2022-10-26 14:48:09 -05:00
wally	FPU divider working with execute stage stall	2022-12-02 11:11:53 -08:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00