forked from Github_Repos/cvw
49 lines
1.7 KiB
Systemverilog
49 lines
1.7 KiB
Systemverilog
///////////////////////////////////////////
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// irom.sv
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//
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// Written: Ross Thompson ross1728@gmail.com January 30, 2022
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// Modified:
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//
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// Purpose: simple instruction ROM
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// A component of the CORE-V Wally configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module irom(
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input logic clk, ce,
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input logic [`XLEN-1:0] Adr,
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output logic [31:0] ReadData
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);
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localparam ADDR_WDITH = $clog2(`IROM_RANGE/8);
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localparam OFFSET = $clog2(`XLEN/8);
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logic [`XLEN-1:0] ReadDataFull;
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rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataFull));
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if (`XLEN == 32) assign ReadData = ReadDataFull;
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// have to delay Ardr[OFFSET-1] by 1 cycle
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else begin
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logic AdrD;
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flopen #(1) AdrReg(clk, ce, Adr[OFFSET-1], AdrD);
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assign ReadData = AdrD ? ReadDataFull[63:32] : ReadDataFull[31:0];
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end
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endmodule
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