forked from Github_Repos/cvw
42 lines
1.5 KiB
Systemverilog
42 lines
1.5 KiB
Systemverilog
///////////////////////////////////////////
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// aplusbeq0.sv
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//
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// Written: David_Harris@hmc.edu 9/7/2022
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// Modified:
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//
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// Purpose: Determine if A+B = 0. Used in FP divider.
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//
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// A component of the CORE-V Wally configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module aplusbeq0 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] a, b,
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output logic zero);
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logic [WIDTH-1:0] x;
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logic [WIDTH-1:0] orshift;
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// The sum is zero if the bitwise XOR is equal to the bitwise OR shifted left by 1, for all columns
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// *** explain, cite book
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assign x = a ^ b;
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assign orshift = {a[WIDTH-2:0] | b[WIDTH-2:0], 1'b0};
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assign zero = (x == orshift);
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endmodule |