forked from Github_Repos/cvw
114 lines
4.1 KiB
Systemverilog
114 lines
4.1 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtqsel4.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Radix 4 Quotient Digit Selection
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtqsel4 (
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input logic [2:0] Dmsbs,
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input logic [4:0] Smsbs,
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input logic [7:0] WSmsbs, WCmsbs,
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input logic Sqrt, j1,
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output logic [3:0] udigit
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);
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logic [6:0] Wmsbs;
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logic [7:0] PreWmsbs;
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logic [2:0] A;
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assign PreWmsbs = WCmsbs + WSmsbs;
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assign Wmsbs = PreWmsbs[7:1];
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// D = 0001.xxx...
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// Dmsbs = | |
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// W = xxxx.xxx...
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// Wmsbs = | |
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logic [3:0] USel4[1023:0];
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// Prepopulate selection table; this is constant at compile time
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always_comb begin
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integer a, w, i, w2;
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for(a=0; a<8; a++)
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for(w=0; w<128; w++)begin
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i = a*128+w;
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w2 = w-128*(w>=64); // convert to two's complement
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case(a)
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0: if($signed(w2)>=$signed(12)) USel4[i] = 4'b1000;
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else if(w2>=4) USel4[i] = 4'b0100;
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else if(w2>=-4) USel4[i] = 4'b0000;
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else if(w2>=-13) USel4[i] = 4'b0010;
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else USel4[i] = 4'b0001;
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1: if(w2>=14) USel4[i] = 4'b1000;
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else if(w2>=4) USel4[i] = 4'b0100;
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else if(w2>=-4) USel4[i] = 4'b0000;
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else if(w2>=-14) USel4[i] = 4'b0010;
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else USel4[i] = 4'b0001;
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2: if(w2>=16) USel4[i] = 4'b1000;
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else if(w2>=4) USel4[i] = 4'b0100;
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else if(w2>=-6) USel4[i] = 4'b0000;
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else if(w2>=-16) USel4[i] = 4'b0010;
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else USel4[i] = 4'b0001;
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3: if(w2>=16) USel4[i] = 4'b1000;
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else if(w2>=4) USel4[i] = 4'b0100;
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else if(w2>=-6) USel4[i] = 4'b0000;
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else if(w2>=-17) USel4[i] = 4'b0010;
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else USel4[i] = 4'b0001;
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4: if(w2>=18) USel4[i] = 4'b1000;
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else if(w2>=6) USel4[i] = 4'b0100;
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else if(w2>=-6) USel4[i] = 4'b0000;
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else if(w2>=-18) USel4[i] = 4'b0010;
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else USel4[i] = 4'b0001;
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5: if(w2>=20) USel4[i] = 4'b1000;
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else if(w2>=6) USel4[i] = 4'b0100;
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else if(w2>=-8) USel4[i] = 4'b0000;
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else if(w2>=-20) USel4[i] = 4'b0010;
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else USel4[i] = 4'b0001;
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6: if(w2>=20) USel4[i] = 4'b1000;
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else if(w2>=8) USel4[i] = 4'b0100;
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else if(w2>=-8) USel4[i] = 4'b0000;
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else if(w2>=-22) USel4[i] = 4'b0010;
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else USel4[i] = 4'b0001;
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7: if(w2>=24) USel4[i] = 4'b1000;
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else if(w2>=8) USel4[i] = 4'b0100;
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else if(w2>=-8) USel4[i] = 4'b0000;
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else if(w2>=-22) USel4[i] = 4'b0010;
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else USel4[i] = 4'b0001;
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endcase
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end
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end
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// Select A
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always_comb
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if (Sqrt) begin
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if (j1) A = 3'b101;
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else if (Smsbs == 5'b10000) A = 3'b111;
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else A = Smsbs[2:0];
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end else A = Dmsbs;
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// Select quotient digit from lookup table based on A and W
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assign udigit = USel4[{A,Wmsbs}];
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endmodule
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