forked from Github_Repos/cvw
180 lines
7.6 KiB
Systemverilog
180 lines
7.6 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtiter.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtiter(
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input logic clk,
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input logic DivStart,
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input logic DivBusy,
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input logic [`NE-1:0] Xe, Ye,
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input logic XZeroE, YZeroE,
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input logic SqrtE,
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input logic SqrtM,
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input logic [`DIVb+3:0] X,
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input logic [`DIVN-2:0] Dpreproc,
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output logic [`DIVN-2:0] D, // U0.N-1
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output logic [`DIVb+3:0] NextWSN, NextWCN,
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output logic [`DIVb:0] FirstS, FirstSM,
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output logic [`DIVb:0] FirstQ, FirstQM,
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output logic [`DIVb-1:0] FirstC,
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output logic Firstqn,
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output logic [`DIVb+3:0] FirstWS, FirstWC
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);
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//QLEN = 1.(number of bits created for division)
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// N is NF+1 or XLEN
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// WC/WS is dependent on D so 4.N-1 ie N+3 bits or N+2:0 + one more bit in fraction for possible sqrt right shift
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// D is 1.N-1, but the msb is always 1 so 0.N-1 or N-1 bits or N-1:0
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// Dsel should match WC/WS so 4.N-1 ie N+3 bits or N+2:0
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// Q/QM/S/SM should be 1.b so b+1 bits or b:0
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// C needs to be the lenght of the final fraction 0.b so b or b-1:0
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/* verilator lint_off UNOPTFLAT */
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logic [`DIVb+3:0] WSA[`DIVCOPIES-1:0]; // Q4.b
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logic [`DIVb+3:0] WCA[`DIVCOPIES-1:0]; // Q4.b
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logic [`DIVb+3:0] WS[`DIVCOPIES-1:0]; // Q4.b
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logic [`DIVb+3:0] WC[`DIVCOPIES-1:0]; // Q4.b
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logic [`DIVb:0] Q[`DIVCOPIES-1:0]; // U1.b
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logic [`DIVb:0] QM[`DIVCOPIES-1:0];// 1.b
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logic [`DIVb:0] QNext[`DIVCOPIES-1:0];// U1.b
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logic [`DIVb:0] QMNext[`DIVCOPIES-1:0];// U1.b
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logic [`DIVb:0] S[`DIVCOPIES-1:0];// U1.b
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logic [`DIVb:0] SM[`DIVCOPIES-1:0];// U1.b
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logic [`DIVb:0] SNext[`DIVCOPIES-1:0];// U1.b
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logic [`DIVb:0] SMNext[`DIVCOPIES-1:0];// U1.b
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logic [`DIVb-1:0] C[`DIVCOPIES:0]; // 0.b
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logic [`DIVb-1:0] initC; // 0.b
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logic [`DIVCOPIES-1:0] qn;
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/* verilator lint_on UNOPTFLAT */
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logic [`DIVb+3:0] WSN, WCN; // Q4.N-1
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logic [`DIVb+3:0] DBar, D2, DBar2; // Q4.N-1
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logic [`DIVb:0] QMMux;
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logic [`DIVb-1:0] NextC;
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logic [`DIVb-1:0] CMux;
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logic [`DIVb:0] SMux;
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// Top Muxes and Registers
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// When start is asserted, the inputs are loaded into the divider.
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// Otherwise, the divisor is retained and the partial remainder
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// is fed back for the next iteration.
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// - when the start signal is asserted X and 0 are loaded into WS and WC
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// - otherwise load WSA into the flipflop
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// - the assumed one is added to D since it's always normalized (and X/0 is a special case handeled by result selection)
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// - XZeroE is used as the assumed one to avoid creating a sticky bit - all other numbers are normalized
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if (`RADIX == 2) begin : nextw
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assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+2:0], 1'b0};
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assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+2:0], 1'b0};
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// assign NextC = {1'b1, C[`DIVCOPIES-1][`DIVb-1:1]};
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end else begin : nextw
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assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
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assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
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// assign NextC = {2'b11, C[`DIVCOPIES-1][`DIVb-1:2]};
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end
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/*
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if (`RADIX == 2) assign initC = {1'b1, {(`DIVb-1){1'b0}}}; // *** note that these are preshifted right by r compared to book
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else assign initC = {2'b11, {(`DIVb-2){1'b0}}};
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*/
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assign initC = 0;
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// mux2 #(`DIVb+4) wsmux(NextWSN, {3'b0, X}, DivStart, WSN);
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mux2 #(`DIVb+4) wsmux(NextWSN, X, DivStart, WSN);
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flopen #(`DIVb+4) wsflop(clk, DivStart|DivBusy, WSN, WS[0]);
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mux2 #(`DIVb+4) wcmux(NextWCN, '0, DivStart, WCN);
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flopen #(`DIVb+4) wcflop(clk, DivStart|DivBusy, WCN, WC[0]);
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flopen #(`DIVN-1) dflop(clk, DivStart, Dpreproc, D);
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mux2 #(`DIVb) Cmux(C[`DIVCOPIES], initC, DivStart, CMux);
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flopen #(`DIVb) cflop(clk, DivStart|DivBusy, CMux, C[0]);
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// Divisor Selections
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// - choose the negitive version of what's being selected
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// - D is only the fraction
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assign DBar = {3'b111, 1'b0, ~D, {`DIVb-`DIVN+1{1'b1}}};
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if(`RADIX == 4) begin : d2
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assign DBar2 = {2'b11, 1'b0, ~D, {`DIVb+2-`DIVN{1'b1}}};
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assign D2 = {2'b0, 1'b1, D, {`DIVb+2-`DIVN{1'b0}}};
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end
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genvar i;
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generate
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for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : interations
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if (`RADIX == 2) begin: stage
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fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM,
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.WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]),
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.C(C[i]), .S(S[i]), .SM(SM[i]), .CNext(C[i+1]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i]));
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end else begin: stage
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logic j1;
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assign j1 = (i == 0 & C[0][`DIVb-2] & ~C[0][`DIVb-3]);
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fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, .j1,
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.WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]),
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.C(C[i]), .S(S[i]), .SM(SM[i]), .CNext(C[i+1]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i]));
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end
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if(i<(`DIVCOPIES-1)) begin
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if (`RADIX==2)begin
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assign WS[i+1] = {WSA[i][`DIVb+2:0], 1'b0};
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assign WC[i+1] = {WCA[i][`DIVb+2:0], 1'b0};
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// assign C[i+1] = {1'b1, C[i][`DIVb-1:1]};
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end else begin
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assign WS[i+1] = {WSA[i][`DIVb+1:0], 2'b0};
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assign WC[i+1] = {WCA[i][`DIVb+1:0], 2'b0};
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// assign C[i+1] = {2'b11, C[i][`DIVb-1:2]};
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end
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assign Q[i+1] = QNext[i];
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assign QM[i+1] = QMNext[i];
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assign S[i+1] = SNext[i];
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assign SM[i+1] = SMNext[i];
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end
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end
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endgenerate
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// if starting a new divison set Q to 0 and QM to -1
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flopenr #(`DIVb+1) Qreg(clk, DivStart, DivBusy, QNext[`DIVCOPIES-1], Q[0]);
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mux2 #(`DIVb+1) QMmux(QMNext[`DIVCOPIES-1], '1, DivStart, QMMux);
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flopen #(`DIVb+1) QMreg(clk, DivStart|DivBusy, QMMux, QM[0]);
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// if starting new square root, set S to 1 and SM to 0
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flopenr #(`DIVb+1) SMreg(clk, DivStart, DivBusy, SMNext[`DIVCOPIES-1], SM[0]);
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mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {1'b1, {(`DIVb){1'b0}}}, DivStart, SMux);
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flopen #(`DIVb+1) Sreg(clk, DivStart|DivBusy, SMux, S[0]);
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assign FirstWS = WS[0];
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assign FirstWC = WC[0];
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assign FirstS = S[0];
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assign FirstSM = SM[0];
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assign FirstQ = Q[0];
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assign FirstQM = QM[0];
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assign FirstC = C[0];
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assign Firstqn = qn[0];
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endmodule
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