forked from Github_Repos/cvw
29 lines
806 B
Plaintext
29 lines
806 B
Plaintext
# srt.do
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#
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# David_Harris@hmc.edu 19 October 2021
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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}
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vlib work
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vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpacking.sv
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vopt +acc work.testbench -o workopt
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vsim workopt
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-- display input and output signals as hexidecimal values
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do ./srt-waves.do
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-- Run the Simulation
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run -all
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