forked from Github_Repos/cvw
16 lines
484 B
Systemverilog
16 lines
484 B
Systemverilog
//leading zero counter i.e. priority encoder
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module lzc #(parameter WIDTH=1) (
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input logic [WIDTH-1:0] num,
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output logic [$clog2(WIDTH)-1:0] ZeroCnt
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);
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/* verilator lint_off CMPCONST */
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logic [$clog2(WIDTH)-1:0] i;
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always_comb begin
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i = 0;
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while (~num[WIDTH-1-(32)'(i)] & $unsigned(i) <= $unsigned(($clog2(WIDTH))'(WIDTH-1))) i = i+1; // search for leading one
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ZeroCnt = i;
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end
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/* verilator lint_on CMPCONST */
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endmodule
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