forked from Github_Repos/cvw
385 lines
13 KiB
Systemverilog
385 lines
13 KiB
Systemverilog
///////////////////////////////////////////
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// dcache (data cache)
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//
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// Written: ross1728@gmail.com July 07, 2021
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// Implements the L1 data cache
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//
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// Purpose: Storage for data and meta data.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module dcache
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(input logic clk,
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input logic reset,
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input logic CPUBusy,
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// cpu side
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic [1:0] AtomicM,
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input logic FlushDCacheM,
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input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits.
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input logic [`PA_BITS-1:0] MemPAdrM, // physical address
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input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM.
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input logic [`XLEN-1:0] WriteDataM,
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output logic [`XLEN-1:0] ReadDataM,
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output logic DCacheStall,
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output logic CommittedM,
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output logic DCacheMiss,
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output logic DCacheAccess,
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// inputs from TLB and PMA/P
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input logic ExceptionM,
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input logic PendingInterruptM,
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input logic CacheableM,
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// from ptw
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input logic IgnoreRequest,
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// ahb side
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(* mark_debug = "true" *)output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
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(* mark_debug = "true" *)output logic AHBRead,
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(* mark_debug = "true" *)output logic AHBWrite,
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(* mark_debug = "true" *)input logic AHBAck, // from ahb
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(* mark_debug = "true" *)input logic [`XLEN-1:0] HRDATA, // from ahb
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(* mark_debug = "true" *)output logic [`XLEN-1:0] HWDATA, // to ahb
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(* mark_debug = "true" *)output logic [2:0] DCtoAHBSizeM
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);
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localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS;
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localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/BLOCKLEN;
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localparam integer NUMWAYS = `DCACHE_NUMWAYS;
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localparam integer BLOCKBYTELEN = BLOCKLEN/8;
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localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN);
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localparam integer INDEXLEN = $clog2(NUMLINES);
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localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
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localparam integer WORDSPERLINE = BLOCKLEN/`XLEN;
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localparam integer LOGWPL = $clog2(WORDSPERLINE);
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localparam integer LOGXLENBYTES = $clog2(`XLEN/8);
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localparam integer FetchCountThreshold = WORDSPERLINE - 1;
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localparam integer FlushAdrThreshold = NUMLINES - 1;
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logic [1:0] SelAdrM;
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logic [INDEXLEN-1:0] RAdr;
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logic [INDEXLEN-1:0] WAdr;
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logic [BLOCKLEN-1:0] SRAMWriteData;
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logic [BLOCKLEN-1:0] DCacheMemWriteData;
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logic SetValid, ClearValid;
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logic SetDirty, ClearDirty;
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logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0];
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logic [NUMWAYS-1:0] WayHit;
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logic CacheHit;
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logic [BLOCKLEN-1:0] ReadDataBlockM;
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logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0];
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logic [`XLEN-1:0] ReadDataWordM, ReadDataWordMuxM;
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logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM;
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logic [LOGWPL-1:0] FetchCount, NextFetchCount;
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logic [WORDSPERLINE-1:0] SRAMWordEnable;
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logic SRAMWordWriteEnableM;
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logic SRAMBlockWriteEnableM;
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logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM;
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//logic SRAMWriteEnable;
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logic [NUMWAYS-1:0] SRAMWayWriteEnable;
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logic [NUMWAYS-1:0] VictimWay;
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logic [NUMWAYS-1:0] VictimDirtyWay;
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logic VictimDirty;
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logic SelUncached;
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logic [2**LOGWPL-1:0] MemPAdrDecodedW;
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logic [`PA_BITS-1:0] BasePAdrM;
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logic [OFFSETLEN-1:0] BasePAdrOffsetM;
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logic [`PA_BITS-1:0] BasePAdrMaskedM;
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logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
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logic [TAGLEN-1:0] VictimTag;
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logic [INDEXLEN-1:0] FlushAdr;
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logic [INDEXLEN-1:0] FlushAdrP1;
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logic FlushAdrCntEn;
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logic FlushAdrCntRst;
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logic FlushAdrFlag;
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logic [NUMWAYS-1:0] FlushWay;
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logic [NUMWAYS-1:0] NextFlushWay;
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logic FlushWayCntEn;
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logic FlushWayCntRst;
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logic SelFlush;
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logic VDWriteEnable;
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logic FetchCountFlag;
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logic CntEn;
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logic CntReset;
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logic SelEvict;
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logic LRUWriteEn;
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logic [NUMWAYS-1:0] VDWriteEnableWay;
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// Read Path CPU (IEU) side
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mux4 #(INDEXLEN)
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AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), // *** REMOVE
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.d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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//.d2(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.d3(FlushAdr),
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.s(SelAdrM),
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.y(RAdr));
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mux2 #(INDEXLEN)
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WAdrSelMux(.d0(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.d1(FlushAdr),
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.s(&SelAdrM),
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.y(WAdr));
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cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
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MemWay[NUMWAYS-1:0](.clk,
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.reset,
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.RAdr,
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.WAdr,
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.PAdr(MemPAdrM),
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.WriteEnable(SRAMWayWriteEnable),
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.VDWriteEnable(VDWriteEnableWay),
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.WriteWordEnable(SRAMWordEnable),
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.TagWriteEnable(SRAMBlockWayWriteEnableM),
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.WriteData(SRAMWriteData),
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.SetValid,
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.ClearValid,
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.SetDirty,
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.ClearDirty,
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.SelEvict,
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.VictimWay,
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.FlushWay,
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.SelFlush,
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.ReadDataBlockWayMasked(ReadDataBlockWayMaskedM),
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.WayHit,
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.VictimDirtyWay,
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.VictimTagWay,
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.InvalidateAll(1'b0));
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generate
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if(NUMWAYS > 1) begin
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cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
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cachereplacementpolicy(.clk, .reset,
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.WayHit,
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.VictimWay,
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.MemPAdrM(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.RAdr,
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.LRUWriteEn);
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end else begin
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assign VictimWay = 1'b1; // one hot.
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end
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endgenerate
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assign CacheHit = | WayHit;
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assign VictimDirty = | VictimDirtyWay;
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// ReadDataBlockWayMaskedM is a 2d array of cache block len by number of ways.
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// Need to OR together each way in a bitwise manner.
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// Final part of the AO Mux. First is the AND in the cacheway.
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or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataBlockWayMaskedM), .y(ReadDataBlockM));
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or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));
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// Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can
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// easily build a variable input mux.
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// *** consider using a limited range shift to do this final muxing.
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genvar index;
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generate
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for (index = 0; index < WORDSPERLINE; index++) begin
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assign ReadDataBlockSetsM[index] = ReadDataBlockM[((index+1)*`XLEN)-1: (index*`XLEN)];
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end
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endgenerate
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// variable input mux
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assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]];
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mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM),
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.d1(DCacheMemWriteData[`XLEN-1:0]),
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.s(SelUncached),
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.y(ReadDataWordMuxM));
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// finally swr
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subwordread subwordread(.ReadDataWordMuxM,
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.MemPAdrM(MemPAdrM[2:0]),
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.Funct3M,
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.ReadDataM);
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// Write Path CPU (IEU) side
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onehotdecoder #(LOGWPL)
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adrdec(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
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.decoded(MemPAdrDecodedW));
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assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW;
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assign SRAMBlockWayWriteEnableM = SRAMBlockWriteEnableM ? VictimWay : '0;
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mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0),
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.d1(SRAMBlockWayWriteEnableM),
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.s(SRAMBlockWriteEnableM),
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.y(SRAMWayWriteEnable));
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generate
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if (`A_SUPPORTED) begin
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logic [`XLEN-1:0] AMOResult;
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amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(Funct3M[1:0]),
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.result(AMOResult));
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mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicM[1], FinalAMOWriteDataM);
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end else
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assign FinalAMOWriteDataM = WriteDataM;
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endgenerate
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subwordwrite subwordwrite(.HRDATA(ReadDataWordM),
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.HADDRD(MemPAdrM[2:0]),
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.HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}),
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.HWDATAIN(FinalAMOWriteDataM),
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.HWDATA(FinalWriteDataM));
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mux2 #(BLOCKLEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteDataM}}),
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.d1(DCacheMemWriteData),
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.s(SRAMBlockWriteEnableM),
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.y(SRAMWriteData));
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// Bus Side logic
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// register the fetch data from the next level of memory.
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// This register should be necessary for timing. There is no register in the uncore or
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// ahblite controller between the memories and this cache.
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generate
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for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
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flopen #(`XLEN) fb(.clk(clk),
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.en(AHBAck & AHBRead & (index == FetchCount)),
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.d(HRDATA),
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.q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
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end
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endgenerate
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mux3 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM),
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.d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
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.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
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.s({SelFlush, SelEvict}),
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.y(BasePAdrM));
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// if not cacheable the offset bits needs to be sent to the EBU.
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// if cacheable the offset bits are discarded. $ FSM will fetch the whole block.
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assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0];
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assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM};
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assign AHBPAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM;
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assign HWDATA = CacheableM | SelFlush ? ReadDataBlockSetsM[FetchCount] : WriteDataM;
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assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]);
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flopenr #(LOGWPL)
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FetchCountReg(.clk(clk),
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.reset(reset | CntReset),
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.en(CntEn),
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.d(NextFetchCount),
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.q(FetchCount));
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assign NextFetchCount = FetchCount + 1'b1;
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// flush address and way generation.
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flopenr #(INDEXLEN)
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FlushAdrReg(.clk,
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.reset(reset | FlushAdrCntRst),
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.en(FlushAdrCntEn & FlushWay[NUMWAYS-1]),
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.d(FlushAdrP1),
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.q(FlushAdr));
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assign FlushAdrP1 = FlushAdr + 1'b1;
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flopenl #(NUMWAYS)
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FlushWayReg(.clk,
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.load(reset | FlushWayCntRst),
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.en(FlushWayCntEn),
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.val({{NUMWAYS-1{1'b0}}, 1'b1}),
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.d(NextFlushWay),
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.q(FlushWay));
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assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}};
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assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
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assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];
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generate
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if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b010 : Funct3M;
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else assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b011 : Funct3M;
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endgenerate;
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//assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM;
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// controller
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dcachefsm dcachefsm(.clk,
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.reset,
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.MemRWM,
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.AtomicM,
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.ExceptionM,
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.PendingInterruptM,
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.CPUBusy,
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.CacheableM,
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.IgnoreRequest,
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.AHBAck, // from ahb
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.CacheHit,
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.FetchCountFlag,
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.VictimDirty,
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.DCacheStall,
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.CommittedM,
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.DCacheMiss,
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.DCacheAccess,
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.AHBRead,
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.AHBWrite,
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.SelAdrM,
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.CntEn,
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.SetValid,
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.ClearValid,
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.SetDirty,
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.ClearDirty,
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.SRAMWordWriteEnableM,
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.SRAMBlockWriteEnableM,
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.CntReset,
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.SelUncached,
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.SelEvict,
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.SelFlush,
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.FlushAdrCntEn,
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.FlushWayCntEn,
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.FlushAdrCntRst,
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.FlushWayCntRst,
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.FlushAdrFlag,
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.FlushDCacheM,
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.VDWriteEnable,
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.LRUWriteEn);
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endmodule // dcache
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