Ross Thompson 8fb5500be8 If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss. ... This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.		2022-01-08 20:49:45 -06:00
..
config	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
fpu-testfloat/FMA/tbgen	Removed more generate statements	2022-01-05 16:25:08 +00:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu	2022-01-07 17:55:34 -06:00
src	If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.	2022-01-08 20:49:45 -06:00
srt	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
testbench	Testbench directory cleanup	2022-01-07 17:02:16 +00:00