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Configurable RISC-V Processor
14 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
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David Harris 8cccfc698d Cleaned up regfile x0 tied to gnd
2021-01-23 21:30:54 -08:00
riscv-o3@afb27bd558 Initial Checkin 2021-01-14 23:37:51 -05:00
wally-pipelined Cleaned up regfile x0 tied to gnd 2021-01-23 21:30:54 -08:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor