forked from Github_Repos/cvw
91 lines
3.9 KiB
Systemverilog
91 lines
3.9 KiB
Systemverilog
///////////////////////////////////////////
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// uart.sv
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//
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// Written: David_Harris@hmc.edu 21 January 2021
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// Modified:
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//
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// Purpose: Interface to Universial Asynchronous Receiver/ Transmitter with FIFOs
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// Emulates interface of Texas Instruments PC165550D
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// Compatible with UART in Imperas Virtio model ***
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module uart (
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input logic HCLK, HRESETn,
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input logic HSELUART,
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input logic [2:0] HADDR,
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input logic HWRITE,
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input logic [`XLEN-1:0] HWDATA,
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output logic [`XLEN-1:0] HREADUART,
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output logic HRESPUART, HREADYUART,
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(* mark_debug = "true" *) input logic SIN, DSRb, DCDb, CTSb, RIb, // from E1A driver from RS232 interface
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(* mark_debug = "true" *) output logic SOUT, RTSb, DTRb, // to E1A driver to RS232 interface
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(* mark_debug = "true" *) output logic OUT1b, OUT2b, INTR, TXRDYb, RXRDYb); // to CPU
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// UART interface signals
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logic [2:0] A;
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logic MEMRb, MEMWb, memread, memwrite;
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logic [7:0] Din, Dout;
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// rename processor interface signals to match PC16550D and provide one-byte interface
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flopr #(1) memreadreg(HCLK, ~HRESETn, (HSELUART & ~HWRITE), memread);
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flopr #(1) memwritereg(HCLK, ~HRESETn, (HSELUART & HWRITE), memwrite);
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flopr #(3) haddrreg(HCLK, ~HRESETn, HADDR[2:0], A);
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assign MEMRb = ~memread;
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assign MEMWb = ~memwrite;
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assign HRESPUART = 0; // OK
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assign HREADYUART = 1; // should idle high during address phase and respond high when done; will need to be modified if UART ever needs more than 1 cycle to do something
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generate
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if (`XLEN == 64) begin
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always_comb begin
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HREADUART = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
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case (A)
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3'b000: Din = HWDATA[7:0];
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3'b001: Din = HWDATA[15:8];
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3'b010: Din = HWDATA[23:16];
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3'b011: Din = HWDATA[31:24];
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3'b100: Din = HWDATA[39:32];
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3'b101: Din = HWDATA[47:40];
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3'b110: Din = HWDATA[55:48];
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3'b111: Din = HWDATA[63:56];
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endcase
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end
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end else begin // 32-bit
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always_comb begin
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HREADUART = {Dout, Dout, Dout, Dout};
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case (A[1:0])
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2'b00: Din = HWDATA[7:0];
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2'b01: Din = HWDATA[15:8];
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2'b10: Din = HWDATA[23:16];
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2'b11: Din = HWDATA[31:24];
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endcase
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end
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end
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endgenerate
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logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK
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// *** make sure reads don't occur on UART unless fully selected because they could change state. This applies to all peripherals
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uartPC16550D u(.RCLK(BAUDOUTb), .*);
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endmodule
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