bbracker 2322e66f9f fix lint bugs in PLIC and UART		2022-02-22 05:04:18 +00:00
..
config	change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests	2022-02-22 03:46:08 +00:00
fpu-testfloat/FMA/tbgen	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests	2022-02-22 03:46:08 +00:00
src	fix lint bugs in PLIC and UART	2022-02-22 05:04:18 +00:00
srt	Moved order of reading a, b, and result from test vectors file so that result	2022-02-21 17:28:11 +00:00
testbench	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-22 04:27:50 +00:00