forked from Github_Repos/cvw
82 lines
3.3 KiB
Systemverilog
82 lines
3.3 KiB
Systemverilog
///////////////////////////////////////////
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// tlbram.sv
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//
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// Written: jtorrey@hmc.edu & tfleming@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Stores page table entries of cached address translations.
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// Outputs the physical page number and access bits of the current
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// virtual address on a TLB hit.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module tlbram #(parameter ENTRY_BITS = 3) (
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input logic clk, reset,
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//input logic [ENTRY_BITS-1:0] VPNIndex, // Index to read from
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// input logic [ENTRY_BITS-1:0] WriteIndex, // *** unused?
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input logic [`XLEN-1:0] PTEWriteVal,
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// input logic TLBWrite,
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input logic [2**ENTRY_BITS-1:0] ReadLines, WriteEnables,
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output logic [`PPN_BITS-1:0] PhysicalPageNumber,
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output logic [7:0] PTEAccessBits
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);
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localparam NENTRIES = 2**ENTRY_BITS;
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//logic [`XLEN-1:0] ram[NENTRIES-1:0];
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logic [`XLEN-1:0] RamRead[NENTRIES-1:0];
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logic [`XLEN-1:0] PageTableEntry;
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// logic [ENTRY_BITS-1:0] VPNIndex;
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// Generate a flop for every entry in the RAM
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//flopenr #(`XLEN) pteflops[NENTRIES-1:0](clk, reset, WriteEnables, PTEWriteVal, ram);
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tlbramline #(`XLEN) tlblineram[NENTRIES-1:0](clk, reset, ReadLines, WriteEnables, PTEWriteVal, RamRead);
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/*
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// temporary code for read
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// verilator lint_off WIDTH
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integer i;
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generate
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always_comb begin
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VPNIndex = 0;
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for (i=0; i<NENTRIES; i++)
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if (ReadLines[i]) VPNIndex = i;
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end
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endgenerate
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// verilator lint_on WIDTH
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*/
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//assign PageTableEntry = ram[VPNIndex]; // *** need to fix
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assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE
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assign PTEAccessBits = PageTableEntry[7:0];
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assign PhysicalPageNumber = PageTableEntry[`PPN_BITS+9:10];
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endmodule
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module tlbramline #(parameter WIDTH)
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(input logic clk, reset,
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input logic re, we,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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logic [WIDTH-1:0] line;
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flopenr #(`XLEN) pteflop(clk, reset, we, d, line);
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assign q = re ? line : 0;
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endmodule |