forked from Github_Repos/cvw
62 lines
2.1 KiB
Systemverilog
62 lines
2.1 KiB
Systemverilog
///////////////////////////////////////////
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// clockgater.sv
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//
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// Written: Ross Thompson 9 January 2021
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// Modified:
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//
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// Purpose: Clock gater model. Must use standard cell for synthesis.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module clockgater
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(input logic E,
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input logic SE,
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input logic CLK,
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output logic ECLK);
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if (`FPGA) begin
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BUFGCE bufgce_i0 (
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.I(CLK),
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.CE(E | SE),
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.O(ECLK)
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);
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end else begin
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// *** BUG
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// VERY IMPORTANT.
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// This part functionally models a clock gater, but does not necessarily meet the timing constrains a real standard cell would.
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// Do not use this in synthesis!
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logic enable_q;
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always_latch begin
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if(~CLK) begin
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enable_q <= E | SE;
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end
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end
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assign ECLK = enable_q & CLK;
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end
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endmodule
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