forked from Github_Repos/cvw
82 lines
1.5 KiB
Systemverilog
Executable File
82 lines
1.5 KiB
Systemverilog
Executable File
//
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// File name : tb.v
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// Title : stimulus
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// project : ECEN3233
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// Library : test
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// Author(s) : James E. Stine, Jr.
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// Purpose : definition of modules for testbench
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// notes :
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//
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// Copyright Oklahoma State University
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//
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module stimulus();
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logic clk;
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// Declare variables for stimulating input
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logic [31:0] rdata;
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logic wfull;
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logic rempty;
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logic [31:0] wdata;
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logic winc, wclk, wrst_n;
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logic rinc, rclk, rrst_n;
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logic [31:0] vectornum;
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logic [31:0] errors;
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integer handle3;
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integer desc3;
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integer i;
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integer j;
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// Instantiate the design block counter
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fifo #(32,4) dut (rdata, wfull, rempty,
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wdata, winc, clk, wrst_n,
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rinc, clk, rrst_n);
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// Setup the clock to toggle every 1 time units
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initial
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begin
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clk = 1'b1;
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forever #5 clk = ~clk;
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end
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initial
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begin
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// Gives output file name
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handle3 = $fopen("test.out");
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rrst_n = 1'b0;
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wrst_n = 1'b0;
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end
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initial
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begin
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#43 rrst_n = 1'b1;
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#0 wrst_n = 1'b1;
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for (j=0; j < 16; j=j+1)
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begin
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// Put vectors before beginning of clk
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@(posedge clk)
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begin
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wdata = $random;
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winc = $random;
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end
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@(negedge clk)
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begin
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vectornum = vectornum + 1;
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end // @(negedge clk)
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end // for (i=0; i < 16; i=i+1)
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$display("%d tests completed with %d errors", vectornum, errors);
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$finish;
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end // initial begin
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endmodule // stimulus
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