forked from Github_Repos/cvw
79 lines
3.4 KiB
Systemverilog
79 lines
3.4 KiB
Systemverilog
///////////////////////////////////////////
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// amoalu.sv
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//
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// Written: David_Harris@hmc.edu 10 March 2021
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// Modified:
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//
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// Purpose: Performs AMO operations
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module amoalu (
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input logic [`XLEN-1:0] srca, srcb,
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input logic [6:0] funct,
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input logic [1:0] width,
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output logic [`XLEN-1:0] result);
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logic [`XLEN-1:0] a, b, y;
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// *** can this be muxed into the regular ALU to avoid needing a second one? Only a good
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// idea if the regular ALU is not the critical path
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// *** see how synthesis generates this and optimize more structurally if necessary to share hardware
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// a single carry chain should be shared for + and the four min/max
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// and the same mux can be used to select b for swap.
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always_comb
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case (funct[6:2])
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5'b00001: y = b; // amoswap
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5'b00000: y = a + b; // amoadd
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5'b00100: y = a ^ b; // amoxor
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5'b01100: y = a & b; // amoand
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5'b01000: y = a | b; // amoor
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5'b10000: y = ($signed(a) < $signed(b)) ? a : b; // amomin
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5'b10100: y = ($signed(a) >= $signed(b)) ? a : b; // amomax
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5'b11000: y = ($unsigned(a) < $unsigned(b)) ? a : b; // amominu
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5'b11100: y = ($unsigned(a) >= $unsigned(b)) ? a : b; // amomaxu
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default: y = 'bx; // undefined; *** could change to b for efficiency
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endcase
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// sign extend if necessary
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generate
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if (`XLEN == 32) begin
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assign a = srca;
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assign b = srcb;
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assign result = y;
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end else begin // `XLEN = 64
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always_comb
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if (width == 2'b10) begin // sign-extend word-length operations
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// *** it would be more efficient to look at carry out of bit 31 to determine comparisons than do this big mux on and b
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a = {{32{srca[31]}}, srca[31:0]};
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b = {{32{srcb[31]}}, srcb[31:0]};
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result = {{32{y[31]}}, y[31:0]};
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end else begin
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a = srca;
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b = srcb;
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result = y;
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end
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end
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endgenerate
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endmodule
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