forked from Github_Repos/cvw
57 lines
2.1 KiB
Systemverilog
57 lines
2.1 KiB
Systemverilog
///////////////////////////////////////////
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// atomic.sv
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//
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// Written: Ross Thompson ross1728@gmail.com January 31, 2022
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// Modified:
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//
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// Purpose: atomic data path.
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module atomic (
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input logic clk,
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input logic reset, StallW,
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input logic [`XLEN-1:0] ReadDataM,
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input logic [`XLEN-1:0] IHWriteDataM,
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input logic [`PA_BITS-1:0] PAdrM,
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input logic [6:0] LSUFunct7M,
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input logic [2:0] LSUFunct3M,
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input logic [1:0] LSUAtomicM,
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input logic [1:0] PreLSURWM,
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input logic IgnoreRequest,
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output logic [`XLEN-1:0] IMAWriteDataM,
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output logic SquashSCW,
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output logic [1:0] LSURWM
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);
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logic [`XLEN-1:0] AMOResult;
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logic MemReadM;
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amoalu amoalu(.srca(ReadDataM), .srcb(IHWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]),
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.result(AMOResult));
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mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResult, LSUAtomicM[1], IMAWriteDataM);
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assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
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lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
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endmodule
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