forked from Github_Repos/cvw
66 lines
2.6 KiB
Systemverilog
66 lines
2.6 KiB
Systemverilog
///////////////////////////////////////////
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// forward.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Determine datapath forwarding
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module forward(
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// Detect hazards
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input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
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input logic MemReadE, MDUE, CSRReadE,
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input logic RegWriteM, RegWriteW,
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input logic FWriteIntE,
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input logic SCE,
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// Forwarding controls
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output logic [1:0] ForwardAE, ForwardBE,
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output logic FPUStallD, LoadStallD, MDUStallD, CSRRdStallD
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);
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logic MatchDE;
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always_comb begin
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ForwardAE = 2'b00;
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ForwardBE = 2'b00;
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if (Rs1E != 5'b0)
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if ((Rs1E == RdM) & RegWriteM) ForwardAE = 2'b10;
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else if ((Rs1E == RdW) & RegWriteW) ForwardAE = 2'b01;
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if (Rs2E != 5'b0)
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if ((Rs2E == RdM) & RegWriteM) ForwardBE = 2'b10;
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else if ((Rs2E == RdW) & RegWriteW) ForwardBE = 2'b01;
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end
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// Stall on dependent operations that finish in Mem Stage and can't bypass in time
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assign MatchDE = (Rs1D == RdE) | (Rs2D == RdE); // Decode-stage instruction source depends on result from execute stage instruction
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assign FPUStallD = FWriteIntE & MatchDE;
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assign LoadStallD = (MemReadE|SCE) & MatchDE;
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assign MDUStallD = MDUE & MatchDE;
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assign CSRRdStallD = CSRReadE & MatchDE;
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endmodule
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