forked from Github_Repos/cvw
89 lines
3.5 KiB
Systemverilog
89 lines
3.5 KiB
Systemverilog
///////////////////////////////////////////
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// alu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: RISC-V Arithmetic/Logic Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module alu #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B,
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input logic [2:0] ALUControl,
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input logic [2:0] Funct3,
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output logic [WIDTH-1:0] Result,
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output logic [WIDTH-1:0] Sum);
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logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
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logic Right;
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logic Carry, Neg;
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logic LT, LTU;
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logic Overflow;
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logic W64, SubArith, ALUOp;
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logic [2:0] ALUFunct;
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// Extract control signals
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// W64 indicates RV64 W-suffix instructions acting on lower 32-bit word
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// SubArith indicates subtraction
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// ALUOp = 0 for address generation addition or 1 for regular ALU
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assign {W64, SubArith, ALUOp} = ALUControl;
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// addition
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assign CondInvB = SubArith ? ~B : B;
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assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
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// Shifts
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assign Right = Funct3[2]; // sra or srl
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shifter sh(A, B[`LOG_XLEN-1:0], Right, SubArith, W64, Shift);
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// condition code flags based on add/subtract output
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// Overflow occurs when the numbers being added have the same sign
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// and the result has the opposite sign
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assign Overflow = (A[WIDTH-1] ~^ CondInvB[WIDTH-1]) & (A[WIDTH-1] ^ Sum[WIDTH-1]);
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assign Neg = Sum[WIDTH-1];
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assign LT = Neg ^ Overflow;
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assign LTU = ~Carry;
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// SLT
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assign SLT = {{(WIDTH-1){1'b0}}, LT};
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assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
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// Select appropriate ALU Result
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assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
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always_comb
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casez (ALUFunct)
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3'b000: FullResult = Sum; // add or sub
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3'b?01: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = SLT; // slt
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3'b011: FullResult = SLTU; // sltu
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3'b100: FullResult = A ^ B; // xor
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3'b110: FullResult = A | B; // or
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3'b111: FullResult = A & B; // and
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endcase
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// support W-type RV64I ADDW/SUBW/ADDIW/Shifts that sign-extend 32-bit result to 64 bits
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generate
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if (WIDTH==64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign Result = FullResult;
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endgenerate
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endmodule
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