Configurable RISC-V Processor
Go to file
2021-12-08 01:03:02 -08:00
addins FMA uses one LOA 2021-12-07 14:15:43 -08:00
benchmarks/riscv-coremark Coremark updates 2021-11-30 11:16:13 -08:00
bin exe2memfile don't print when only 1 file 2021-11-18 20:37:53 -08:00
fpga Added information on how to copy the linux image to flash card. 2021-12-07 13:16:38 -06:00
tests Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
wally-pipelined Removed .*s from wally-pipelined/src/uncore/uncore.sv 2021-12-08 01:03:02 -08:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-04 20:26:01 -08:00
.gitmodules added arch-test submodule 2021-11-30 18:22:08 -08:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
Makefile Added files to repo 2021-12-04 20:25:33 -08:00
README.md changed readme to reflect submodule updates 2021-11-30 18:26:49 -08:00
wally-setup.sh Added files to repo 2021-12-04 20:25:33 -08:00

riscv-wally

Configurable RISC-V Processor

Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.

To use Wally on Linux:

git clone https://github.com/davidharrishmc/riscv-wally --recurse-submodules
cd riscv-wally
cd addins
cd riscv-isa-sim
*** replace these with a copy from ../install/F and ../install/D containing the Makefile.includes already updated
cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F
<edit arch_test_target/spike/device/rv32i_m/F/Makefile.include line 35 and change --isa=rv32i to --isa=rv32if>
cp -r arch_test_target/spike/device/rv64i_m/I arch_test_target/spike/device/rv64i_m/D
<edit arch_test_target/spike/device/rv64i_m/D/Makefile.include line 35 and change --isa=rv64i to --isa=rv64id>
mkdir build
cd build
set RISCV=/cad/riscv/gcc/bin   (or whatever your path is)
../configure --prefix=$RISCV
make (this will take a while to build SPIKE)
sudo make install
cd ../../riscv-arch-test
cp ../riscv-isa-sim/arch_test_target/spike/Makefile.include .
edit Makefile.include
  change line with TARGETDIR to /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target (or whatever your path is) 
  add line export RISCV_PREFIX = riscv64-unknown-elf-  # this might not be needed if you have 32-bit versions of the riscv gcc compiler built separately
make
make XLEN=32
exe2memfile.pl work/*/*/*.elf  # converts ELF files to a format that can be read by Modelsim
cd ../../tests
cd imperas-riscv-tests
make
cd ../wally-riscv-arch-test
make
make XLEN=32
exe2memfile.pl work/*/*/*.elf  # converts ELF files to a format that can be read by Modelsim
cd ../linux-testgen/linux-testvectors
./tvLinker.sh

Notes: Eventually download imperas-riscv-tests separately Move our custom tests to another directory Eventually replace exe2memfile.pl with objcopy