forked from Github_Repos/cvw
62 lines
2.4 KiB
Systemverilog
62 lines
2.4 KiB
Systemverilog
///////////////////////////////////////////
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// mul.sv
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//
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// Written: David_Harris@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Integer multiplication
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//
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// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.18)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module mul(
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input logic clk, reset,
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input logic StallM, FlushM,
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // source A and B from after Forwarding mux
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input logic [2:0] Funct3E, // type of multiply
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output logic [`XLEN*2-1:0] ProdM // double-widthproduct
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);
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logic [`XLEN*2-1:0] PP1E, PP2E, PP3E, PP4E; // partial products
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logic [`XLEN*2-1:0] PP1M, PP2M, PP3M, PP4M; // registered partial proudcts
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//////////////////////////////
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// Execute Stage: Compute partial products
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//////////////////////////////
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// insert stuff here for lab 5
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//////////////////////////////
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// Memory Stage: Sum partial proudcts
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//////////////////////////////
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flopenrc #(`XLEN*2) PP1Reg(clk, reset, FlushM, ~StallM, PP1E, PP1M);
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flopenrc #(`XLEN*2) PP2Reg(clk, reset, FlushM, ~StallM, PP2E, PP2M);
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flopenrc #(`XLEN*2) PP3Reg(clk, reset, FlushM, ~StallM, PP3E, PP3M);
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flopenrc #(`XLEN*2) PP4Reg(clk, reset, FlushM, ~StallM, PP4E, PP4M);
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// add up partial products; this multi-input add implies CSAs and a final CPA
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assign ProdM = PP1M + PP2M + PP3M + PP4M; //ForwardedSrcAE * ForwardedSrcBE;
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endmodule
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