forked from Github_Repos/cvw
141 lines
5.3 KiB
Systemverilog
141 lines
5.3 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtiter.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: k stages of divsqrt logic, plus registers
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtiter(
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input logic clk,
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input logic IFDivStartE,
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input logic FDivBusyE,
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input logic SqrtE,
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input logic [`DIVb+3:0] X,
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input logic [`DIVb-1:0] DPreproc,
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output logic [`DIVb-1:0] D,
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output logic [`DIVb:0] FirstU, FirstUM,
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output logic [`DIVb+1:0] FirstC,
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output logic Firstun,
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output logic [`DIVb+3:0] FirstWS, FirstWC
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);
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/* verilator lint_off UNOPTFLAT */
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logic [`DIVb+3:0] WSNext[`DIVCOPIES-1:0]; // Q4.b
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logic [`DIVb+3:0] WCNext[`DIVCOPIES-1:0]; // Q4.b
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logic [`DIVb+3:0] WS[`DIVCOPIES:0]; // Q4.b
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logic [`DIVb+3:0] WC[`DIVCOPIES:0]; // Q4.b
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logic [`DIVb:0] U[`DIVCOPIES:0]; // U1.b
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logic [`DIVb:0] UM[`DIVCOPIES:0]; // U1.b
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logic [`DIVb:0] UNext[`DIVCOPIES-1:0]; // U1.b
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logic [`DIVb:0] UMNext[`DIVCOPIES-1:0]; // U1.b
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logic [`DIVb+1:0] C[`DIVCOPIES:0]; // Q2.b
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logic [`DIVb+1:0] initC; // Q2.b
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logic [`DIVCOPIES-1:0] un;
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logic [`DIVb+3:0] WSN, WCN; // Q4.b
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logic [`DIVb+3:0] DBar, D2, DBar2; // Q4.b
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logic [`DIVb+1:0] NextC;
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logic [`DIVb:0] UMux, UMMux;
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logic [`DIVb:0] initU, initUM;
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/* verilator lint_on UNOPTFLAT */
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// Top Muxes and Registers
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// When start is asserted, the inputs are loaded into the divider.
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// Otherwise, the divisor is retained and the residual and result
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// are fed back for the next iteration.
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// Residual WS/SC registers/initializaiton mux
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mux2 #(`DIVb+4) wsmux(WS[`DIVCOPIES], X, IFDivStartE, WSN);
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mux2 #(`DIVb+4) wcmux(WC[`DIVCOPIES], '0, IFDivStartE, WCN);
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flopen #(`DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]);
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flopen #(`DIVb+4) wcreg(clk, FDivBusyE, WCN, WC[0]);
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// UOTFC Result U and UM registers/initialization mux
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// Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 otherwise
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assign initU = {SqrtE, {(`DIVb){1'b0}}};
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assign initUM = {~SqrtE, {(`DIVb){1'b0}}};
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mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, IFDivStartE, UMux);
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mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, IFDivStartE, UMMux);
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flopen #(`DIVb+1) UReg(clk, IFDivStartE|FDivBusyE, UMux, U[0]);
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flopen #(`DIVb+1) UMReg(clk, IFDivStartE|FDivBusyE, UMMux, UM[0]);
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// C register/initialization mux
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// Initialize C to -1 for sqrt and -R for division
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logic [1:0] initCUpper;
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if(`RADIX == 4) begin
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mux2 #(2) cuppermux4(2'b00, 2'b11, SqrtE, initCUpper);
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end else begin
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mux2 #(2) cuppermux2(2'b10, 2'b11, SqrtE, initCUpper);
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end
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assign initC = {initCUpper, {`DIVb{1'b0}}};
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mux2 #(`DIVb+2) cmux(C[`DIVCOPIES], initC, IFDivStartE, NextC);
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flopen #(`DIVb+2) creg(clk, IFDivStartE|FDivBusyE, NextC, C[0]);
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// Divisior register
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flopen #(`DIVb) dreg(clk, IFDivStartE, DPreproc, D);
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// Divisor Selections
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// - choose the negitive version of what's being selected
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// - D is a 0.b mantissa
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assign DBar = {3'b111, 1'b0, ~D};
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if(`RADIX == 4) begin : d2
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assign DBar2 = {2'b11, 1'b0, ~D, 1'b1};
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assign D2 = {2'b0, 1'b1, D, 1'b0};
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end
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// k=DIVCOPIES of the recurrence logic
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genvar i;
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generate
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for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : iterations
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if (`RADIX == 2) begin: stage
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fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtE,
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.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
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.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
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end else begin: stage
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logic j1;
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assign j1 = (i == 0 & ~C[0][`DIVb-1]);
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fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1,
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.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
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.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
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end
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assign WS[i+1] = WSNext[i];
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assign WC[i+1] = WCNext[i];
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assign U[i+1] = UNext[i];
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assign UM[i+1] = UMNext[i];
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end
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endgenerate
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// Send values from start of cycle for postprocessing
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assign FirstWS = WS[0];
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assign FirstWC = WC[0];
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assign FirstU = U[0];
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assign FirstUM = UM[0];
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assign FirstC = C[0];
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assign Firstun = un[0];
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endmodule
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