forked from Github_Repos/cvw
49 lines
1.6 KiB
Systemverilog
49 lines
1.6 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtfgen2.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Radix 2 F Addend Generator
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtfgen2 (
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input logic up, uz,
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input logic [`DIVb+3:0] C, U, UM,
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output logic [`DIVb+3:0] F
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);
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logic [`DIVb+3:0] FP, FN, FZ;
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// Generate for both positive and negative bits
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assign FP = ~(U << 1) & C;
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assign FN = (UM << 1) | (C & ~(C << 2));
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assign FZ = '0;
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always_comb // Choose which adder input will be used
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if (up) F = FP;
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else if (uz) F = FZ;
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else F = FN;
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endmodule
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