forked from Github_Repos/cvw
92 lines
3.8 KiB
Systemverilog
92 lines
3.8 KiB
Systemverilog
///////////////////////////////////////////
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// pmpadrdec.sv
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//
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// Written: tfleming@hmc.edu 28 April 2021
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// Modified:
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//
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// Purpose: Address decoder for the PMP checker. Decides whether a given address
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// falls within the PMP range for each address-matching mode
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// (top-of-range/TOR, naturally aligned four-byte region/NA4, and
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// naturally aligned power-of-two region/NAPOT), then selects the
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// output based on which mode is input.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module pmpadrdec (
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input logic [`PA_BITS-1:0] PhysicalAddress,
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input logic [7:0] PMPCfg,
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input logic [`XLEN-1:0] PMPAdr,
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input logic PAgePMPAdrIn,
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output logic PAgePMPAdrOut,
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output logic Match, Active,
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output logic L, X, W, R
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);
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localparam TOR = 2'b01;
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localparam NA4 = 2'b10;
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localparam NAPOT = 2'b11;
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logic TORMatch, NAMatch;
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logic PAltPMPAdr;
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logic [`PA_BITS-1:0] CurrentAdrFull;
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logic [1:0] AdrMode;
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assign AdrMode = PMPCfg[4:3];
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// The two lsb of the physical address don't matter for this checking.
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// The following code includes them, but hardwires the PMP checker lsbs to 00
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// and masks them later. Logic synthesis should optimize away these bottom bits.
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// Top-of-range (TOR)
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// Append two implicit trailing 0's to PMPAdr value
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assign CurrentAdrFull = {PMPAdr[`PA_BITS-3:0], 2'b00};
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assign PAltPMPAdr = {1'b0, PhysicalAddress} < {1'b0, CurrentAdrFull}; // unsigned comparison
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assign PAgePMPAdrOut = ~PAltPMPAdr;
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assign TORMatch = PAgePMPAdrIn & PAltPMPAdr;
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// Naturally aligned regions
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logic [`PA_BITS-1:0] NAMask, NABase;
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assign NAMask[1:0] = {2'b11};
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assign NAMask[`PA_BITS-1:2] = (PMPAdr[`PA_BITS-3:0] + {{(`PA_BITS-3){1'b0}}, (AdrMode == NAPOT)}) ^ PMPAdr[`PA_BITS-3:0];
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// form a mask where the bottom k bits are 1, corresponding to a size of 2^k bytes for this memory region.
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// This assumes we're using at least an NA4 region, but works for any size NAPOT region.
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assign NABase = {(PMPAdr[`PA_BITS-3:0] & ~NAMask[`PA_BITS-1:2]), 2'b00}; // base physical address of the pmp.
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assign NAMatch = &((NABase ~^ PhysicalAddress) | NAMask); // check if upper bits of base address match, ignore lower bits correspoonding to inside the memory range
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assign Match = (AdrMode == TOR) ? TORMatch :
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(AdrMode == NA4 | AdrMode == NAPOT) ? NAMatch :
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0;
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assign L = PMPCfg[7];
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assign X = PMPCfg[2];
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assign W = PMPCfg[1];
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assign R = PMPCfg[0];
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assign Active = |PMPCfg[4:3];
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endmodule
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