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Configurable RISC-V Processor
1,570 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
7b9e53fbe5
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Ross Thompson 7b9e53fbe5 Removed 1 cycle delay on store miss. 
Changed some logic to partially support atomics.
2021-07-30 14:00:51 -05:00
riscv-coremark Updated location to find compiler for coremark 2021-07-16 19:13:18 -04:00
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined Removed 1 cycle delay on store miss. 2021-07-30 14:00:51 -05:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor