cvw/pipelined/src
Ross Thompson c4a9354c13 Replaced PCLinkX registers with a +2/4 adder in the execution stage.
David and I estimate this is lower hardware cost.
2023-02-03 18:19:47 -06:00
..
cache Comment cleanup in subcachelineread 2023-01-28 11:00:05 -08:00
ebu Removed integer from localparams 2023-01-27 14:40:06 -08:00
fpu Clean up tabs 2023-01-15 18:23:09 -08:00
generic Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22 2023-02-02 13:54:25 -06:00
hazard Fixed bug #47 discovered by Lee Moore. 2023-02-02 08:52:06 -06:00
ieu Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED 2023-01-28 18:52:00 -08:00
ifu Replaced PCLinkX registers with a +2/4 adder in the execution stage. 2023-02-03 18:19:47 -06:00
lsu Lee Moore found another bug using imperas. 2023-02-02 23:52:21 -06:00
mdu MDU comment cleanup 2023-01-12 07:15:14 -08:00
mmu Imperas found a real bug in virtual memory. 2023-01-30 11:47:51 -06:00
privileged Fixed bug #49. 2023-02-03 00:39:26 -06:00
uncore Removed mark_debug from all source code. 2023-01-20 18:47:36 -06:00
wally Restored top-level modules without import statements 2023-01-30 12:54:40 -08:00