forked from Github_Repos/cvw
25 lines
886 B
Verilog
25 lines
886 B
Verilog
// fma16.sv
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// David_Harris@hmc.edu 26 February 2022
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// 16-bit floating-point multiply-accumulate
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// Operation: general purpose multiply, add, fma, with optional negation
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// If mul=1, p = x * y. Else p = x.
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// If add=1, result = p + z. Else result = p.
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// If negr or negz = 1, negate result or z to handle negations and subtractions
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// fadd: mul = 0, add = 1, negr = negz = 0
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// fsub: mul = 0, add = 1, negr = 0, negz = 1
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// fmul: mul = 1, add = 0, negr = 0, negz = 0
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// fmadd: mul = 1, add = 1, negr = 0, negz = 0
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// fmsub: mul = 1, add = 1, negr = 0, negz = 1
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// fnmadd: mul = 1, add = 1, negr = 1, negz = 0
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// fnmsub: mul = 1, add = 1, negr = 1, negz = 1
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module fma16(
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input logic [15:0] x, y, z,
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input logic mul, add, negr, negz,
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input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn
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output logic [15:0] result);
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endmodule
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