Ross Thompson 76bba541a7 Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.		2021-10-24 21:21:49 -05:00
..
cachereplacementpolicy.sv	Lint cleanup	2021-10-23 09:06:21 -07:00
cacheway.sv	Partial cleanup of unused signals in caches and bpred.	2021-10-24 15:04:20 -05:00
dcache_ptw_interaction_README.txt	Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm.	2021-08-27 11:03:36 -05:00
dcache.sv	Partial cleanup of unused signals in caches and bpred.	2021-10-24 15:04:20 -05:00
dcachefsm.sv	replaced flopenl with flopenr when clearing to 0	2021-10-18 16:53:18 -07:00
icache.sv	Partial cleanup of unused signals in caches and bpred.	2021-10-24 15:04:20 -05:00
icachefsm.sv	Partial cleanup of unused signals in caches and bpred.	2021-10-24 15:04:20 -05:00
sram1rw.sv	Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.	2021-10-24 21:21:49 -05:00