forked from Github_Repos/cvw
1007 lines
27 KiB
Systemverilog
1007 lines
27 KiB
Systemverilog
// ppa.sv
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// Teo Ene & David_Harris@hmc.edu 11 May 2022
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// & mmasserfrye@hmc.edu
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// Measure PPA of various building blocks
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module ppa_comparator_8 #(parameter WIDTH=8) (
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input logic [WIDTH-1:0] a, b,
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input logic sgnd,
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output logic [1:0] flags);
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ppa_comparator #(WIDTH) comp (.*);
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endmodule
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module ppa_comparator_16 #(parameter WIDTH=16) (
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input logic [WIDTH-1:0] a, b,
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input logic sgnd,
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output logic [1:0] flags);
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ppa_comparator #(WIDTH) comp (.*);
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endmodule
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module ppa_comparator_32 #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] a, b,
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input logic sgnd,
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output logic [1:0] flags);
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ppa_comparator #(WIDTH) comp (.*);
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endmodule
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module ppa_comparator_64 #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] a, b,
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input logic sgnd,
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output logic [1:0] flags);
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ppa_comparator #(WIDTH) comp (.*);
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endmodule
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module ppa_comparator_128 #(parameter WIDTH=128) (
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input logic [WIDTH-1:0] a, b,
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input logic sgnd,
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output logic [1:0] flags);
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ppa_comparator #(WIDTH) comp (.*);
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endmodule
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module ppa_comparator #(parameter WIDTH=16) (
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input logic [WIDTH-1:0] a, b,
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input logic sgnd,
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output logic [1:0] flags);
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logic eq, lt, ltu;
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logic [WIDTH-1:0] af, bf;
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// For signed numbers, flip most significant bit
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assign af = {a[WIDTH-1] ^ sgnd, a[WIDTH-2:0]};
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assign bf = {b[WIDTH-1] ^ sgnd, b[WIDTH-2:0]};
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// behavioral description gives best results
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assign eq = (af == bf);
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assign lt = (af < bf);
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assign flags = {eq, lt};
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endmodule
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module ppa_add_8 #(parameter WIDTH=8) (
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH-1:0] y);
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assign y = a + b;
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endmodule
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module ppa_add_16 #(parameter WIDTH=16) (
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH-1:0] y);
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assign y = a + b;
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endmodule
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module ppa_add_32 #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH-1:0] y);
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assign y = a + b;
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endmodule
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module ppa_add_64 #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH-1:0] y);
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assign y = a + b;
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endmodule
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module ppa_add_128 #(parameter WIDTH=128) (
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH-1:0] y);
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assign y = a + b;
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endmodule
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module ppa_mult_8 #(parameter WIDTH=8) (
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH*2-1:0] y); //is this right width
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assign y = a * b;
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endmodule
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module ppa_mult_16 #(parameter WIDTH=16) (
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH*2-1:0] y); //is this right width
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assign y = a * b;
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endmodule
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module ppa_mult_32 #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH*2-1:0] y); //is this right width
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assign y = a * b;
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endmodule
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module ppa_mult_64 #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH*2-1:0] y); //is this right width
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assign y = a * b;
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endmodule
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module ppa_mult_128 #(parameter WIDTH=128) (
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH*2-1:0] y); //is this right width
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assign y = a * b;
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endmodule
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module ppa_alu_8 #(parameter WIDTH=8) (
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input logic [WIDTH-1:0] A, B,
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input logic [2:0] ALUControl,
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input logic [2:0] Funct3,
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output logic [WIDTH-1:0] Result,
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output logic [WIDTH-1:0] Sum);
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ppa_alu #(WIDTH) alu (.*);
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endmodule
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module ppa_alu_16 #(parameter WIDTH=16) (
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input logic [WIDTH-1:0] A, B,
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input logic [2:0] ALUControl,
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input logic [2:0] Funct3,
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output logic [WIDTH-1:0] Result,
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output logic [WIDTH-1:0] Sum);
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ppa_alu #(WIDTH) alu (.*);
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endmodule
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module ppa_alu_32 #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B,
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input logic [2:0] ALUControl,
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input logic [2:0] Funct3,
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output logic [WIDTH-1:0] Result,
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output logic [WIDTH-1:0] Sum);
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ppa_alu #(WIDTH) alu (.*);
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endmodule
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module ppa_alu_64 #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] A, B,
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input logic [2:0] ALUControl,
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input logic [2:0] Funct3,
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output logic [WIDTH-1:0] Result,
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output logic [WIDTH-1:0] Sum);
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ppa_alu #(WIDTH) alu (.*);
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endmodule
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module ppa_alu_128 #(parameter WIDTH=128) (
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input logic [WIDTH-1:0] A, B,
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input logic [2:0] ALUControl,
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input logic [2:0] Funct3,
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output logic [WIDTH-1:0] Result,
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output logic [WIDTH-1:0] Sum);
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ppa_alu #(WIDTH) alu (.*);
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endmodule
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module ppa_alu #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B,
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input logic [2:0] ALUControl,
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input logic [2:0] Funct3,
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output logic [WIDTH-1:0] Result,
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output logic [WIDTH-1:0] Sum);
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logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
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logic Carry, Neg;
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logic LT, LTU;
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logic W64, SubArith, ALUOp;
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logic [2:0] ALUFunct;
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logic Asign, Bsign;
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// Extract control signals
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// W64 indicates RV64 W-suffix instructions acting on lower 32-bit word
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// SubArith indicates subtraction
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// ALUOp = 0 for address generation addition or 1 for regular ALU
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assign {W64, SubArith, ALUOp} = ALUControl;
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// addition
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assign CondInvB = SubArith ? ~B : B;
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assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
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// Shifts
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ppa_shifter #(WIDTH) sh(.A, .Amt(B[$clog2(WIDTH)-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
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// condition code flags based on subtract output Sum = A-B
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// Overflow occurs when the numbers being subtracted have the opposite sign
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// and the result has the opposite sign of A
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assign Neg = Sum[WIDTH-1];
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assign Asign = A[WIDTH-1];
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assign Bsign = B[WIDTH-1];
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assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; // simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow
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assign LTU = ~Carry;
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// SLT
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assign SLT = {{(WIDTH-1){1'b0}}, LT};
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assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
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// Select appropriate ALU Result
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assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
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always_comb
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casez (ALUFunct)
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3'b000: FullResult = Sum; // add or sub
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3'b?01: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = SLT; // slt
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3'b011: FullResult = SLTU; // sltu
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3'b100: FullResult = A ^ B; // xor
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3'b110: FullResult = A | B; // or
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3'b111: FullResult = A & B; // and
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endcase
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assign Result = FullResult;
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// not using W64 so it has the same architecture regardless of width
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// // support W-type RV64I ADDW/SUBW/ADDIW/Shifts that sign-extend 32-bit result to 64 bits
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// if (WIDTH==64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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// else assign Result = FullResult;
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endmodule
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module ppa_shiftleft_8 #(parameter WIDTH=8) (
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input logic [WIDTH-1:0] a,
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input logic [$clog2(WIDTH)-1:0] amt,
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output logic [WIDTH-1:0] y);
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assign y = a << amt;
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endmodule
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module ppa_shiftleft_16 #(parameter WIDTH=16) (
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input logic [WIDTH-1:0] a,
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input logic [$clog2(WIDTH)-1:0] amt,
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output logic [WIDTH-1:0] y);
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assign y = a << amt;
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endmodule
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module ppa_shiftleft_32 #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] a,
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input logic [$clog2(WIDTH)-1:0] amt,
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output logic [WIDTH-1:0] y);
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assign y = a << amt;
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endmodule
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module ppa_shiftleft_64 #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] a,
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input logic [$clog2(WIDTH)-1:0] amt,
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output logic [WIDTH-1:0] y);
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assign y = a << amt;
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endmodule
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module ppa_shiftleft_128 #(parameter WIDTH=128) (
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input logic [WIDTH-1:0] a,
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input logic [$clog2(WIDTH)-1:0] amt,
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output logic [WIDTH-1:0] y);
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assign y = a << amt;
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endmodule
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module ppa_shifter #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A,
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input logic [$clog2(WIDTH)-1:0] Amt,
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input logic Right, Arith, W64,
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output logic [WIDTH-1:0] Y);
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logic [2*WIDTH-2:0] z, zshift;
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logic [$clog2(WIDTH)-1:0] amttrunc, offset;
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// Handle left and right shifts with a funnel shifter.
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// For RV32, only 32-bit shifts are needed.
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// For RV64, 32 and 64-bit shifts are needed, with sign extension.
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// funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
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// if (WIDTH == 64 | WIDTH ==128) begin:shifter // RV64 or 128
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// always_comb // funnel mux
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// if (W64) begin // 32-bit shifts
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// if (Right)
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// if (Arith) z = {{WIDTH{1'b0}}, {WIDTH/2 -1{A[WIDTH/2 -1]}}, A[WIDTH/2 -1:0]};
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// else z = {{WIDTH*3/2-1{1'b0}}, A[WIDTH/2 -1:0]};
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// else z = {{WIDTH/2{1'b0}}, A[WIDTH/2 -1:0], {WIDTH-1{1'b0}}};
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// end else begin
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// if (Right)
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// if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A};
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// else z = {{WIDTH-1{1'b0}}, A};
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// else z = {A, {WIDTH-1{1'b0}}};
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// end
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// assign amttrunc = W64 ? {1'b0, Amt[$clog2(WIDTH)-2:0]} : Amt; // 32 or 64-bit shift
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// end else begin:shifter // RV32 or less
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// always_comb // funnel mux
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// if (Right)
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// if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A};
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// else z = {{WIDTH-1{1'b0}}, A};
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// else z = {A, {WIDTH-1{1'b0}}};
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// assign amttrunc = Amt; // shift amount
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// end
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always_comb // funnel mux
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if (Right)
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if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A};
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else z = {{WIDTH-1{1'b0}}, A};
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else z = {A, {WIDTH-1{1'b0}}};
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assign amttrunc = Amt; // shift amount
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// opposite offset for right shfits
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assign offset = Right ? amttrunc : ~amttrunc;
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// funnel operation
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assign zshift = z >> offset;
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assign Y = zshift[WIDTH-1:0];
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endmodule
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// module ppa_shifter_8 #(parameter WIDTH=8) (
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// input logic [WIDTH-1:0] A,
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// input logic [$clog2(WIDTH)-1:0] Amt,
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// input logic Right, Arith, W64,
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// output logic [WIDTH-1:0] Y);
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// ppa_shifter #(WIDTH) sh (.*);
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// endmodule
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// module ppa_shifter_16 #(parameter WIDTH=16) (
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// input logic [WIDTH-1:0] A,
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// input logic [$clog2(WIDTH)-1:0] Amt,
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// input logic Right, Arith, W64,
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// output logic [WIDTH-1:0] Y);
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// ppa_shifter #(WIDTH) sh (.*);
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// endmodule
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// module ppa_shifter_32 #(parameter WIDTH=32) (
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// input logic [WIDTH-1:0] A,
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// input logic [$clog2(WIDTH)-1:0] Amt,
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// input logic Right, Arith, W64,
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// output logic [WIDTH-1:0] Y);
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// ppa_shifter #(WIDTH) sh (.*);
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// endmodule
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// module ppa_shifter_64 #(parameter WIDTH=64) (
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// input logic [WIDTH-1:0] A,
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// input logic [$clog2(WIDTH)-1:0] Amt,
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// input logic Right, Arith, W64,
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// output logic [WIDTH-1:0] Y);
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// ppa_shifter #(WIDTH) sh (.*);
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// endmodule
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// module ppa_shifter_128 #(parameter WIDTH=128) (
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// input logic [WIDTH-1:0] A,
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// input logic [$clog2(WIDTH)-1:0] Amt,
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// input logic Right, Arith, W64,
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// output logic [WIDTH-1:0] Y);
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// ppa_shifter #(WIDTH) sh (.*);
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// endmodule
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module ppa_prioritythermometer #(parameter N = 8) (
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input logic [N-1:0] a,
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output logic [N-1:0] y);
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// Carefully crafted so design compiler will synthesize into a fast tree structure
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// Rather than linear.
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// create thermometer code mask
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genvar i;
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assign y[0] = ~a[0];
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for (i=1; i<N; i++) begin:therm
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assign y[i] = y[i-1] & ~a[i];
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end
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endmodule
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module ppa_priorityonehot #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] a,
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output logic [WIDTH-1:0] y);
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logic [WIDTH-1:0] nolower;
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// create thermometer code mask
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ppa_prioritythermometer #(WIDTH) maskgen(.a({a[WIDTH-2:0], 1'b0}), .y(nolower));
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assign y = a & nolower;
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endmodule
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module ppa_priorityonehot_8 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] a,
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output logic [WIDTH-1:0] y);
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logic [WIDTH-1:0] nolower;
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// create thermometer code mask
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ppa_priorityonehot #(WIDTH) poh (.*);
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endmodule
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module ppa_priorityonehot_16 #(parameter WIDTH = 16) (
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input logic [WIDTH-1:0] a,
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output logic [WIDTH-1:0] y);
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logic [WIDTH-1:0] nolower;
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// create thermometer code mask
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ppa_priorityonehot #(WIDTH) poh (.*);
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endmodule
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module ppa_priorityonehot_32 #(parameter WIDTH = 32) (
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input logic [WIDTH-1:0] a,
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output logic [WIDTH-1:0] y);
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logic [WIDTH-1:0] nolower;
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// create thermometer code mask
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ppa_priorityonehot #(WIDTH) poh (.*);
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endmodule
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module ppa_priorityonehot_64 #(parameter WIDTH = 64) (
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input logic [WIDTH-1:0] a,
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output logic [WIDTH-1:0] y);
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logic [WIDTH-1:0] nolower;
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// create thermometer code mask
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ppa_priorityonehot #(WIDTH) poh (.*);
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endmodule
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module ppa_priorityonehot_128 #(parameter WIDTH = 128) (
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input logic [WIDTH-1:0] a,
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output logic [WIDTH-1:0] y);
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logic [WIDTH-1:0] nolower;
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// create thermometer code mask
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ppa_priorityonehot #(WIDTH) poh (.*);
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endmodule
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module ppa_priorityencoder_8 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] a,
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output logic [$clog2(WIDTH)-1:0] y);
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ppa_priorityencoder #(WIDTH) pe (.*);
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endmodule
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module ppa_priorityencoder_16 #(parameter WIDTH = 16) (
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input logic [WIDTH-1:0] a,
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output logic [$clog2(WIDTH)-1:0] y);
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ppa_priorityencoder #(WIDTH) pe (.*);
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endmodule
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module ppa_priorityencoder_32 #(parameter WIDTH = 32) (
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input logic [WIDTH-1:0] a,
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output logic [$clog2(WIDTH)-1:0] y);
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ppa_priorityencoder #(WIDTH) pe (.*);
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endmodule
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module ppa_priorityencoder_64 #(parameter WIDTH = 64) (
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input logic [WIDTH-1:0] a,
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output logic [$clog2(WIDTH)-1:0] y);
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ppa_priorityencoder #(WIDTH) pe (.*);
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endmodule
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module ppa_priorityencoder_128 #(parameter WIDTH = 128) (
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input logic [WIDTH-1:0] a,
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output logic [$clog2(WIDTH)-1:0] y);
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ppa_priorityencoder #(WIDTH) pe (.*);
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endmodule
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module ppa_priorityencoder #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] a,
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output logic [$clog2(WIDTH)-1:0] y);
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int i;
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always_comb begin
|
|
y = 0;
|
|
for (i=0; i<WIDTH; i++) begin:pri
|
|
if (a[i]) y= i;
|
|
end
|
|
end
|
|
endmodule
|
|
|
|
module ppa_decoder_8 #(parameter WIDTH = 8) (
|
|
input logic [$clog2(WIDTH)-1:0] a,
|
|
output logic [WIDTH-1:0] y);
|
|
ppa_decoder #(WIDTH) dec (.*);
|
|
endmodule
|
|
|
|
module ppa_decoder_16 #(parameter WIDTH = 16) (
|
|
input logic [$clog2(WIDTH)-1:0] a,
|
|
output logic [WIDTH-1:0] y);
|
|
ppa_decoder #(WIDTH) dec (.*);
|
|
endmodule
|
|
|
|
module ppa_decoder_32 #(parameter WIDTH = 32) (
|
|
input logic [$clog2(WIDTH)-1:0] a,
|
|
output logic [WIDTH-1:0] y);
|
|
ppa_decoder #(WIDTH) dec (.*);
|
|
endmodule
|
|
|
|
module ppa_decoder_64 #(parameter WIDTH = 64) (
|
|
input logic [$clog2(WIDTH)-1:0] a,
|
|
output logic [WIDTH-1:0] y);
|
|
ppa_decoder #(WIDTH) dec (.*);
|
|
endmodule
|
|
|
|
module ppa_decoder_128 #(parameter WIDTH = 128) (
|
|
input logic [$clog2(WIDTH)-1:0] a,
|
|
output logic [WIDTH-1:0] y);
|
|
ppa_decoder #(WIDTH) dec (.*);
|
|
endmodule
|
|
|
|
module ppa_decoder #(parameter WIDTH = 8) (
|
|
input logic [$clog2(WIDTH)-1:0] a,
|
|
output logic [WIDTH-1:0] y);
|
|
always_comb begin
|
|
y = 0;
|
|
y[a] = 1;
|
|
end
|
|
endmodule
|
|
|
|
module ppa_mux2d_1 #(parameter WIDTH = 1) (
|
|
input logic [WIDTH-1:0] d0, d1,
|
|
input logic s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s ? d1 : d0;
|
|
endmodule
|
|
|
|
module ppa_mux4d_1 #(parameter WIDTH = 1) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3,
|
|
input logic [1:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
|
|
endmodule
|
|
|
|
module ppa_mux8d_1 #(parameter WIDTH = 1) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
|
|
input logic [2:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
|
|
endmodule
|
|
|
|
module ppa_mux2_1 #(parameter WIDTH = 1) (
|
|
input logic [WIDTH-1:0] d0, d1,
|
|
input logic s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s ? d1 : d0;
|
|
endmodule
|
|
|
|
module ppa_mux4_1 #(parameter WIDTH = 1) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3,
|
|
input logic [1:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
|
|
endmodule
|
|
|
|
module ppa_mux8_1 #(parameter WIDTH = 1) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
|
|
input logic [2:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
|
|
endmodule
|
|
|
|
module ppa_mux2_8 #(parameter WIDTH = 8) (
|
|
input logic [WIDTH-1:0] d0, d1,
|
|
input logic s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s ? d1 : d0;
|
|
endmodule
|
|
|
|
module ppa_mux4_8 #(parameter WIDTH = 8) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3,
|
|
input logic [1:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
|
|
endmodule
|
|
|
|
module ppa_mux8_8 #(parameter WIDTH = 8) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
|
|
input logic [2:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
|
|
endmodule
|
|
|
|
module ppa_mux2_16 #(parameter WIDTH = 16) (
|
|
input logic [WIDTH-1:0] d0, d1,
|
|
input logic s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s ? d1 : d0;
|
|
endmodule
|
|
|
|
module ppa_mux4_16 #(parameter WIDTH = 16) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3,
|
|
input logic [1:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
|
|
endmodule
|
|
|
|
module ppa_mux8_16 #(parameter WIDTH = 16) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
|
|
input logic [2:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
|
|
endmodule
|
|
|
|
module ppa_mux2_32 #(parameter WIDTH = 32) (
|
|
input logic [WIDTH-1:0] d0, d1,
|
|
input logic s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s ? d1 : d0;
|
|
endmodule
|
|
|
|
module ppa_mux4_32 #(parameter WIDTH = 32) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3,
|
|
input logic [1:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
|
|
endmodule
|
|
|
|
module ppa_mux8_32 #(parameter WIDTH = 32) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
|
|
input logic [2:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
|
|
endmodule
|
|
|
|
module ppa_mux2_64 #(parameter WIDTH = 64) (
|
|
input logic [WIDTH-1:0] d0, d1,
|
|
input logic s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s ? d1 : d0;
|
|
endmodule
|
|
|
|
module ppa_mux4_64 #(parameter WIDTH = 64) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3,
|
|
input logic [1:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
|
|
endmodule
|
|
|
|
module ppa_mux8_64 #(parameter WIDTH = 64) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
|
|
input logic [2:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
|
|
endmodule
|
|
|
|
module ppa_mux2_128 #(parameter WIDTH = 128) (
|
|
input logic [WIDTH-1:0] d0, d1,
|
|
input logic s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s ? d1 : d0;
|
|
endmodule
|
|
|
|
module ppa_mux4_128 #(parameter WIDTH = 128) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3,
|
|
input logic [1:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
|
|
endmodule
|
|
|
|
module ppa_mux8_128 #(parameter WIDTH = 128) (
|
|
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
|
|
input logic [2:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
|
|
endmodule
|
|
|
|
// *** some way to express data-critical inputs
|
|
|
|
module ppa_flop #(parameter WIDTH = 8) (
|
|
input logic clk,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
always_ff @(posedge clk)
|
|
q <= #1 d;
|
|
endmodule
|
|
|
|
module ppa_flop_8 #(parameter WIDTH = 8) (
|
|
input logic clk,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flop #(WIDTH) f1(clk, d, q1);
|
|
ppa_flop #(WIDTH) f2(clk, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flop_16 #(parameter WIDTH = 16) (
|
|
input logic clk,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flop #(WIDTH) f1(clk, d, q1);
|
|
ppa_flop #(WIDTH) f2(clk, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flop_32 #(parameter WIDTH = 32) (
|
|
input logic clk,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flop #(WIDTH) f1(clk, d, q1);
|
|
ppa_flop #(WIDTH) f2(clk, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flop_64 #(parameter WIDTH = 64) (
|
|
input logic clk,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flop #(WIDTH) f1(clk, d, q1);
|
|
ppa_flop #(WIDTH) f2(clk, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flop_128 #(parameter WIDTH = 128) (
|
|
input logic clk,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flop #(WIDTH) f1(clk, d, q1);
|
|
ppa_flop #(WIDTH) f2(clk, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flopr #(parameter WIDTH = 8) (
|
|
input logic clk, reset,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
always_ff @(posedge clk)
|
|
if (reset) q <= #1 0;
|
|
else q <= #1 d;
|
|
endmodule
|
|
|
|
module ppa_flopr_8 #(parameter WIDTH = 8) (
|
|
input logic clk, reset,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flopr #(WIDTH) f1(clk, reset, d, q1);
|
|
ppa_flopr #(WIDTH) f2(clk, reset, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flopr_16 #(parameter WIDTH = 16) (
|
|
input logic clk, reset,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flopr #(WIDTH) f1(clk, reset, d, q1);
|
|
ppa_flopr #(WIDTH) f2(clk, reset, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flopr_32 #(parameter WIDTH = 32) (
|
|
input logic clk, reset,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flopr #(WIDTH) f1(clk, reset, d, q1);
|
|
ppa_flopr #(WIDTH) f2(clk, reset, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flopr_64 #(parameter WIDTH = 64) (
|
|
input logic clk, reset,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flopr #(WIDTH) f1(clk, reset, d, q1);
|
|
ppa_flopr #(WIDTH) f2(clk, reset, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flopr_128 #(parameter WIDTH = 128) (
|
|
input logic clk, reset,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flopr #(WIDTH) f1(clk, reset, d, q1);
|
|
ppa_flopr #(WIDTH) f2(clk, reset, q1, q);
|
|
endmodule
|
|
|
|
module ppa_floprasync #(parameter WIDTH = 8) (
|
|
input logic clk, reset,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
always_ff @(posedge clk or posedge reset)
|
|
if (reset) q <= #1 0;
|
|
else q <= #1 d;
|
|
endmodule
|
|
|
|
module ppa_floprasync_8 #(parameter WIDTH = 8) (
|
|
input logic clk, reset,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_floprasync #(WIDTH) f1(clk, reset, d, q1);
|
|
ppa_floprasync #(WIDTH) f2(clk, reset, q1, q);
|
|
endmodule
|
|
|
|
module ppa_floprasync_16 #(parameter WIDTH = 16) (
|
|
input logic clk, reset,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_floprasync #(WIDTH) f1(clk, reset, d, q1);
|
|
ppa_floprasync #(WIDTH) f2(clk, reset, q1, q);
|
|
endmodule
|
|
|
|
module ppa_floprasync_32 #(parameter WIDTH = 32) (
|
|
input logic clk, reset,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_floprasync #(WIDTH) f1(clk, reset, d, q1);
|
|
ppa_floprasync #(WIDTH) f2(clk, reset, q1, q);
|
|
endmodule
|
|
|
|
module ppa_floprasync_64 #(parameter WIDTH = 64) (
|
|
input logic clk, reset,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_floprasync #(WIDTH) f1(clk, reset, d, q1);
|
|
ppa_floprasync #(WIDTH) f2(clk, reset, q1, q);
|
|
endmodule
|
|
|
|
module ppa_floprasync_128 #(parameter WIDTH = 128) (
|
|
input logic clk, reset,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_floprasync #(WIDTH) f1(clk, reset, d, q1);
|
|
ppa_floprasync #(WIDTH) f2(clk, reset, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flopenr #(parameter WIDTH = 8) (
|
|
input logic clk, reset, en,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
always_ff @(posedge clk)
|
|
if (reset) q <= #1 0;
|
|
else if (en) q <= #1 d;
|
|
endmodule
|
|
|
|
module ppa_flopenr_8 #(parameter WIDTH = 8) (
|
|
input logic clk, reset, en,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flopenr #(WIDTH) f1(clk, reset, en, d, q1);
|
|
ppa_flopenr #(WIDTH) f2(clk, reset, en, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flopenr_16 #(parameter WIDTH = 16) (
|
|
input logic clk, reset, en,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flopenr #(WIDTH) f1(clk, reset, en, d, q1);
|
|
ppa_flopenr #(WIDTH) f2(clk, reset, en, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flopenr_32 #(parameter WIDTH = 32) (
|
|
input logic clk, reset, en,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flopenr #(WIDTH) f1(clk, reset, en, d, q1);
|
|
ppa_flopenr #(WIDTH) f2(clk, reset, en, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flopenr_64 #(parameter WIDTH = 64) (
|
|
input logic clk, reset, en,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
logic [WIDTH-1:0] q1;
|
|
|
|
ppa_flopenr #(WIDTH) f1(clk, reset, en, d, q1);
|
|
ppa_flopenr #(WIDTH) f2(clk, reset, en, q1, q);
|
|
endmodule
|
|
|
|
module ppa_flopenr_128 #(parameter WIDTH = 128) (
|
|
input logic clk, reset, en,
|
|
input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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logic [WIDTH-1:0] q1;
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ppa_flopenr #(WIDTH) f1(clk, reset, en, d, q1);
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ppa_flopenr #(WIDTH) f2(clk, reset, en, q1, q);
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endmodule
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module ppa_csa_8 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] a, b, c,
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output logic [WIDTH-1:0] sum, carry);
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assign sum = a ^ b ^ c;
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assign carry = (a & (b | c)) | (b & c);
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endmodule
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module ppa_csa_16 #(parameter WIDTH = 16) (
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input logic [WIDTH-1:0] a, b, c,
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output logic [WIDTH-1:0] sum, carry);
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|
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assign sum = a ^ b ^ c;
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assign carry = (a & (b | c)) | (b & c);
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|
endmodule
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module ppa_csa_32 #(parameter WIDTH = 32) (
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input logic [WIDTH-1:0] a, b, c,
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output logic [WIDTH-1:0] sum, carry);
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|
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assign sum = a ^ b ^ c;
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assign carry = (a & (b | c)) | (b & c);
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|
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|
endmodule
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module ppa_csa_64 #(parameter WIDTH = 64) (
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|
input logic [WIDTH-1:0] a, b, c,
|
|
output logic [WIDTH-1:0] sum, carry);
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|
|
|
assign sum = a ^ b ^ c;
|
|
assign carry = (a & (b | c)) | (b & c);
|
|
|
|
endmodule
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module ppa_csa_128 #(parameter WIDTH = 128) (
|
|
input logic [WIDTH-1:0] a, b, c,
|
|
output logic [WIDTH-1:0] sum, carry);
|
|
|
|
assign sum = a ^ b ^ c;
|
|
assign carry = (a & (b | c)) | (b & c);
|
|
|
|
endmodule
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module ppa_inv_1 #(parameter WIDTH = 1) (
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input logic [WIDTH-1:0] a,
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|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = ~a;
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|
endmodule |