forked from Github_Repos/cvw
55 lines
2.2 KiB
Systemverilog
55 lines
2.2 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtfgen4.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Radix 4 F Addend Generator
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtfgen4 (
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input logic [3:0] udigit,
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input logic [`DIVb+3:0] C, U, UM,
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output logic [`DIVb+3:0] F
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);
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logic [`DIVb+3:0] F2, F1, F0, FN1, FN2;
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// Generate for both positive and negative bits
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assign F2 = (~U << 2) & (C << 2);
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assign F1 = ~(U << 1) & C;
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assign F0 = '0;
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assign FN1 = (UM << 1) | (C & ~(C << 3));
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assign FN2 = (UM << 2) | ((C << 2)&~(C << 4));
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// Choose which adder input will be used
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always_comb
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if (udigit[3]) F = F2;
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else if (udigit[2]) F = F1;
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else if (udigit[1]) F = FN1;
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else if (udigit[0]) F = FN2;
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else F = F0;
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endmodule |