forked from Github_Repos/cvw
100 lines
4.3 KiB
Systemverilog
100 lines
4.3 KiB
Systemverilog
///////////////////////////////////////////
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// uncore.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: System-on-Chip components outside the core (hart)
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// Memories, peripherals, external bus control
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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// *** need idiom to map onto cache RAM with byte writes
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// *** and use memread signal to reduce power when reads aren't needed
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module uncore (
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input logic clk, reset,
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// bus interface
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input logic [1:0] MemRWM,
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input logic [`XLEN-1:0] AdrM, WriteDataM,
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input logic [2:0] Funct3M,
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output logic [`XLEN-1:0] ReadDataM,
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output logic DataAccessFaultM,
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// peripheral pins
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output logic TimerIntM, SwIntM,
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input logic [31:0] GPIOPinsIn,
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output logic [31:0] GPIOPinsOut, GPIOPinsEn,
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input logic UARTSin,
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output logic UARTSout
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);
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logic [`XLEN-1:0] MaskedWriteDataM;
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logic [`XLEN-1:0] ReadDataUnmaskedM;
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logic [`XLEN-1:0] RdTimM, RdCLINTM, RdGPIOM, RdUARTM;
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logic TimEnM, CLINTEnM, GPIOEnM, UARTEnM;
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logic [1:0] MemRWdtimM, MemRWclintM, MemRWgpioM, MemRWuartM;
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logic UARTIntr;// *** will need to tie INTR to an interrupt handler
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// Address decoding
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adrdec timdec(AdrM, `TIMBASE, `TIMRANGE, TimEnM);
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adrdec clintdec(AdrM, `CLINTBASE, `CLINTRANGE, CLINTEnM);
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adrdec gpiodec(AdrM, `GPIOBASE, `GPIORANGE, GPIOEnM);
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adrdec uartdec(AdrM, `UARTBASE, `UARTRANGE, UARTEnM);
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/*// *** generalize, use configurable
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generate
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if (`XLEN == 64)
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assign TimEnM = ~(|AdrM[`XLEN-1:32]) & AdrM[31] & ~(|AdrM[30:19]); // 0x000...80000000 - 0x000...8007FFFF
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else
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assign TimEnM = AdrM[31] & ~(|AdrM[30:19]); // 0x80000000 - 0x8007FFFF
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endgenerate
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assign CLINTEnM = ~(|AdrM[`XLEN-1:26]) & AdrM[25] & ~(|AdrM[24:16]); // 0x02000000-0x0200FFFF
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assign GPIOEnM = (AdrM[31:8] == 24'h10012); // 0x10012000-0x100120FF
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assign UARTEnM = ~(|AdrM[`XLEN-1:29]) & AdrM[28] & ~(|AdrM[27:3]); // 0x10000000-0x10000007
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*/
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// Enable read or write based on decoded address.
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assign MemRWdtimM = MemRWM & {2{TimEnM}};
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assign MemRWclintM = MemRWM & {2{CLINTEnM}};
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assign MemRWgpioM = MemRWM & {2{GPIOEnM}};
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assign MemRWuartM = MemRWM & {2{UARTEnM}};
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// tightly integrated memory
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dtim dtim(.AdrM(AdrM[18:0]), .*);
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// memory-mapped I/O peripherals
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clint clint(.AdrM(AdrM[15:0]), .*);
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gpio gpio(.AdrM(AdrM[7:0]), .*); // *** may want to add GPIO interrupts
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uart uart(.TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout),
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.DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1),
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.RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*);
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// *** Interface to off-chip memory would appear as another peripheral
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// merge reads
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assign ReadDataUnmaskedM = ({`XLEN{TimEnM}} & RdTimM) | ({`XLEN{CLINTEnM}} & RdCLINTM) |
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({`XLEN{GPIOEnM}} & RdGPIOM) | ({`XLEN{UARTEnM}} & RdUARTM);
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assign DataAccessFaultM = ~(TimEnM | CLINTEnM | GPIOEnM | UARTEnM);
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// subword accesses: converts ReadDataUnmaskedM to ReadDataM and WriteDataM to MaskedWriteDataM
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subword subword(.*);
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endmodule
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