forked from Github_Repos/cvw
82 lines
3.2 KiB
Systemverilog
82 lines
3.2 KiB
Systemverilog
///////////////////////////////////////////
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// normshift.sv
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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//
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// Purpose: normalization shifter
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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// convert shift
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// fp -> int: | `XLEN zeros | Mantissa | 0's if nessisary | << CalcExp
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// process:
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// - start - CalcExp = 1 + XExp - Largest Bias
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// | `XLEN zeros | Mantissa | 0's if nessisary |
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//
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// - shift left 1 (1)
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// | `XLEN-1 zeros |bit| frac | 0's if nessisary |
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// . <- binary point
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//
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// - shift left till unbiased exponent is 0 (XExp - Largest Bias)
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// | 0's | Mantissa | 0's if nessisary |
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// | keep |
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//
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// fp -> fp:
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// - if result is subnormal or underflowed:
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// | `NF-1 zeros | Mantissa | 0's if nessisary | << NF+CalcExp-1
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// process:
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// - start
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// | mantissa | 0's |
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//
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// - shift right by NF-1 (NF-1)
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// | `NF-1 zeros | mantissa | 0's |
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//
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// - shift left by CalcExp = XExp - Largest bias + new bias
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// | 0's | mantissa | 0's |
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// | keep |
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//
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// - if the input is subnormal:
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// | lzcIn | 0's if nessisary | << ZeroCnt+1
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// - plus 1 to shift out the first 1
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//
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// int -> fp: | lzcIn | 0's if nessisary | << ZeroCnt+1
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// - plus 1 to shift out the first 1
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// fma shift
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// | 00 | Sm | << LZA output
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// .
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// - two extra bits so we can correct for an LZA error of 1 or 2
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// divsqrt shift
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// | Nf 0's | Qm | << calculated shift amount
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// .
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module normshift(
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input logic [`LOGNORMSHIFTSZ-1:0] ShiftAmt, // shift amount
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input logic [`NORMSHIFTSZ-1:0] ShiftIn, // number to be shifted
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output logic [`NORMSHIFTSZ-1:0] Shifted // shifted result
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);
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assign Shifted = ShiftIn << ShiftAmt;
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endmodule |