forked from Github_Repos/cvw
20 lines
286 B
Systemverilog
20 lines
286 B
Systemverilog
// xz.sv
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// David_Harris@hmc.edu 30 January 2022
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// Demonstrate impact of x and z.
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// load with vsim xz.sv
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module xz(
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output logic w, x, y, z);
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logic p, q, r;
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// let p be undriven
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assign q = 1'bz;
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assign r = 1'bx;
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assign w = q & 1'b1;
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assign x = q | 1'b1;
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endmodule
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