forked from Github_Repos/cvw
95 lines
3.5 KiB
Systemverilog
95 lines
3.5 KiB
Systemverilog
///////////////////////////////////////////
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// testbench-imperas.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Wally Testbench and helper modules
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// Applies test programs from the Imperas suite
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module testbench();
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logic clk;
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logic reset;
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int test, i, errors, totalerrors;
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logic [31:0] sig32[10000:0];
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logic [`XLEN-1:0] signature[10000:0];
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logic [`XLEN-1:0] testadr;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [`XLEN-1:0] meminit;
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string tests[];
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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// pick tests based on modes supported
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initial
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tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.elf.memfile", "1000"};
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string signame, memfilename;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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// instantiate device to be tested
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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assign HREADYEXT = 1;
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assign HRESPEXT = 0;
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assign HRDATAEXT = 0;
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wallypipelinedsoc dut(.*);
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// Track names of instructions
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logic [31:0] InstrW;
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flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.InstrF,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, InstrW,
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// initialize tests
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logic [`XLEN-1:0] PCW;
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flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW);
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integer j;
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initial
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begin
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totalerrors = 0;
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// read test vectors into memory
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memfilename = tests[0];
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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for(j=18710; j < 65535; j = j+1)
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dut.uncore.dtim.RAM[j] = 64'b0;
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reset = 1; # 22; reset = 0;
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end
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// generate clock to sequence tests
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always
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begin
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clk = 1; # 5; clk = 0; # 5;
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end
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endmodule
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/* verilator lint_on STMTDLY */
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/* verilator lint_on WIDTH */
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