forked from Github_Repos/cvw
52 lines
1023 B
Systemverilog
Executable File
52 lines
1023 B
Systemverilog
Executable File
module mux2 #(parameter WIDTH = 8)
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(input logic [WIDTH-1:0] d0, d1,
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input logic s,
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output logic [WIDTH-1:0] y);
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assign y = s ? d1 : d0;
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endmodule // mux2
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module mux3 #(parameter WIDTH = 8)
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(input logic [WIDTH-1:0] d0, d1, d2,
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input logic [1:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[1] ? d2 : (s[0] ? d1 : d0);
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endmodule // mux3
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module mux4 #(parameter WIDTH = 8)
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(input logic [WIDTH-1:0] d0, d1, d2, d3,
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input logic [1:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
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endmodule // mux4
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module mux21x32 (Z, A, B, Sel);
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input logic [31:0] A;
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input logic [31:0] B;
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input logic Sel;
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output logic [31:0] Z;
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assign Z = Sel ? B : A;
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endmodule // mux21x32
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module mux21x64 (Z, A, B, Sel);
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input logic [63:0] A;
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input logic [63:0] B;
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input logic Sel;
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output logic [63:0] Z;
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assign Z = Sel ? B : A;
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endmodule // mux21x64
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