forked from Github_Repos/cvw
356 lines
8.6 KiB
Systemverilog
356 lines
8.6 KiB
Systemverilog
///////////////////////////////////////////////////////
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// srt.sv //
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// //
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// Written 10/31/96 by David Harris harrisd@leland //
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// Updated 10/19/21 David_Harris@hmc.edu //
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// //
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// This file models a simple Radix 2 SRT divider. //
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// //
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///////////////////////////////////////////////////////
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// This Verilog file models a radix 2 SRT divider which
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// produces one quotient digit per cycle. The divider
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// keeps the partial remainder in carry-save form.
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/////////
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// srt //
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/////////
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module srt(input logic clk,
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input logic req,
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input logic sqrt, // 1 to compute sqrt(a), 0 to compute a/b
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input logic [51:0] a, b,
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output logic [54:0] rp, rm);
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// A simple Radix 2 SRT divider/sqrt
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// Internal signals
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logic [55:0] ps, pc; // partial remainder in carry-save form
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logic [55:0] d; // divisor
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logic [55:0] psa, pca; // partial remainder result of csa
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logic [55:0] psn, pcn; // partial remainder for next cycle
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logic [55:0] dn; // divisor for next cycle
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logic [55:0] dsel; // selected divisor multiple
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logic qp, qz, qm; // quotient is +1, 0, or -1
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logic [55:0] d_b; // inverse of divisor
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// Top Muxes and Registers
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// When start is asserted, the inputs are loaded into the divider.
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// Otherwise, the divisor is retained and the partial remainder
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// is fed back for the next iteration.
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mux2 psmux({psa[54:0], 1'b0}, {4'b0001, a}, req, psn);
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flop psflop(clk, psn, ps);
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mux2 pcmux({pca[54:0], 1'b0}, 56'b0, req, pcn);
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flop pcflop(clk, pcn, pc);
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mux2 dmux(d, {4'b0001, b}, req, dn);
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flop dflop(clk, dn, d);
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// Quotient Selection logic
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// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
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// Accumulate quotient digits in a shift register
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qsel qsel(ps[55:52], pc[55:52], qp, qz, qm);
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qacc qacc(clk, req, qp, qz, qm, rp, rm);
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// Divisor Selection logic
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inv dinv(d, d_b);
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mux3 divisorsel(d_b, 56'b0, d, qp, qz, qm, dsel);
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// Partial Product Generation
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csa csa(ps, pc, dsel, qp, psa, pca);
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endmodule
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//////////
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// mux2 //
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//////////
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module mux2(input logic [55:0] in0, in1,
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input logic sel,
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output logic [55:0] out);
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assign #1 out = sel ? in1 : in0;
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endmodule
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//////////
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// flop //
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//////////
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module flop(clk, in, out);
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input clk;
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input [55:0] in;
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output [55:0] out;
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logic [55:0] state;
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always @(posedge clk)
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state <= #1 in;
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assign #1 out = state;
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endmodule
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//////////
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// qsel //
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//////////
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module qsel(input logic [55:52] ps, pc,
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output logic qp, qz, qm);
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logic [55:52] p, g;
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logic magnitude, sign, cout;
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// The quotient selection logic is presented for simplicity, not
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// for efficiency. You can probably optimize your logic to
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// select the proper divisor with less delay.
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// Quotient equations from EE371 lecture notes 13-20
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assign p = ps ^ pc;
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assign g = ps & pc;
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assign #1 magnitude = ~(&p[54:52]);
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assign #1 cout = g[54] | (p[54] & (g[53] | p[53] & g[52]));
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assign #1 sign = p[55] ^ cout;
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/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) &
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(ps[52]^pc[52]));
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assign #1 sign = (ps[55]^pc[55])^
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(ps[54] & pc[54] | ((ps[54]^pc[54]) &
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(ps[53]&pc[53] | ((ps[53]^pc[53]) &
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(ps[52]&pc[52]))))); */
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// Produce quotient = +1, 0, or -1
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assign #1 qp = magnitude & ~sign;
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assign #1 qz = ~magnitude;
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assign #1 qm = magnitude & sign;
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endmodule
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//////////
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// qacc //
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//////////
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module qacc(clk, req, qp, qz, qm, rp, rm);
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input clk;
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input req;
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input qp;
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input qz;
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input qm;
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output [54:0] rp;
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output [54:0] rm;
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logic [54:0] rp, rm; // quotient bit is +/- 1;
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logic [7:0] count;
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always @(posedge clk)
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begin
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if (req)
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begin
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rp <= #1 0;
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rm <= #1 0;
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end
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else
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begin
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rp <= #1 {rp[54:0], qp};
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rm <= #1 {rm[54:0], qm};
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end
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end
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endmodule
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/////////
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// inv //
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/////////
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module inv(input logic [55:0] in,
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output logic [55:0] out);
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assign #1 out = ~in;
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endmodule
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//////////
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// mux3 //
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//////////
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module mux3(in0, in1, in2, sel0, sel1, sel2, out);
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input [55:0] in0;
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input [55:0] in1;
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input [55:0] in2;
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input sel0;
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input sel1;
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input sel2;
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output [55:0] out;
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// lazy inspection of the selects
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// really we should make sure selects are mutually exclusive
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assign #1 out = sel0 ? in0 : (sel1 ? in1 : in2);
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endmodule
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/////////
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// csa //
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/////////
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module csa(in1, in2, in3, cin, out1, out2);
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input [55:0] in1;
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input [55:0] in2;
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input [55:0] in3;
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input cin;
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output [55:0] out1;
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output [55:0] out2;
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// This block adds in1, in2, in3, and cin to produce
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// a result out1 / out2 in carry-save redundant form.
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// cin is just added to the least significant bit and
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// is required to handle adding a negative divisor.
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// Fortunately, the carry (out2) is shifted left by one
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// bit, leaving room in the least significant bit to
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// insert cin.
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assign #1 out1 = in1 ^ in2 ^ in3;
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assign #1 out2 = {in1[54:0] & (in2[54:0] | in3[54:0]) |
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(in2[54:0] & in3[54:0]), cin};
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endmodule
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//////////////
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// finaladd //
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//////////////
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module finaladd(rp, rm, r);
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input [54:0] rp;
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input [54:0] rm;
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output [51:0] r;
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logic [54:0] diff;
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// this magic block performs the final addition for you
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// to convert the positive and negative quotient digits
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// into a normalized mantissa. It returns the 52 bit
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// mantissa after shifting to guarantee a leading 1.
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// You can assume this block operates in one cycle
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// and do not need to budget it in your area and power
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// calculations.
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// Since no rounding is performed, the result may be too
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// small by one unit in the least significant place (ulp).
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// The checker ignores such an error.
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assign #1 diff = rp - rm;
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assign #1 r = diff[54] ? diff[53:2] : diff[52:1];
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endmodule
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/////////////
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// counter //
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/////////////
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module counter(input logic clk,
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input logic req,
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output logic done);
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logic [5:0] count;
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// This block of control logic sequences the divider
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// through its iterations. You may modify it if you
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// build a divider which completes in fewer iterations.
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// You are not responsible for the (trivial) circuit
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// design of the block.
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always @(posedge clk)
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begin
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if (count == 54) done <= #1 1;
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else if (done | req) done <= #1 0;
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if (req) count <= #1 0;
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else count <= #1 count+1;
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end
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endmodule
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///////////
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// clock //
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///////////
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module clock(clk);
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output clk;
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// Internal clk signal
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logic clk;
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endmodule
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//////////
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// testbench //
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//////////
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module testbench;
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logic clk;
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logic req;
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logic done;
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logic [51:0] a;
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logic [51:0] b;
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logic [51:0] r;
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logic [54:0] rp, rm; // positive quotient digits
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// Test parameters
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parameter MEM_SIZE = 40000;
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parameter MEM_WIDTH = 52+52+52;
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`define memr 51:0
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`define memb 103:52
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`define mema 155:104
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// Test logicisters
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logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
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logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a
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// bit field of an array
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logic [51:0] correctr, nextr;
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integer testnum, errors;
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// Divider
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srt srt(clk, req, a, b, rp, rm);
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// Final adder converts quotient digits to 2's complement & normalizes
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finaladd finaladd(rp, rm, r);
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// Counter
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counter counter(clk, req, done);
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initial
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forever
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begin
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clk = 1; #17;
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clk = 0; #16;
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end
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// Read test vectors from disk
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initial
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begin
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testnum = 0;
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errors = 0;
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$readmemh ("testvectors", Tests);
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Vec = Tests[testnum];
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a = Vec[`mema];
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b = Vec[`memb];
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nextr = Vec[`memr];
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req <= #5 1;
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end
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// Apply directed test vectors read from file.
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always @(posedge clk)
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begin
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if (done)
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begin
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req <= #5 1;
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$display("result was %h, should be %h\n", r, correctr);
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if ((correctr - r) > 1) // check if accurate to 1 ulp
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begin
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errors = errors+1;
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$display("failed\n");
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$stop;
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end
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if (a === 52'hxxxxxxxxxxxxx)
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begin
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$display("Tests completed successfully");
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$stop;
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end
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end
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if (req)
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begin
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req <= #5 0;
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correctr = nextr;
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testnum = testnum+1;
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Vec = Tests[testnum];
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$display("a = %h b = %h",a,b);
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a = Vec[`mema];
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b = Vec[`memb];
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nextr = Vec[`memr];
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end
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end
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endmodule
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