forked from Github_Repos/cvw
166 lines
4.0 KiB
ArmAsm
166 lines
4.0 KiB
ArmAsm
// -----------
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// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
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// version : 0.5.1
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// timestamp : Wed Aug 4 06:39:00 2021 GMT
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// usage : riscv_ctg \
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// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
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// --base-isa rv32e \
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// --randomize
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// -----------
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//
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// -----------
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// Copyright (c) 2020. RISC-V International. All rights reserved.
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the c.addi4spn instruction of the RISC-V C extension for the caddi4spn covergroup.
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//
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV32EC")
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",caddi4spn)
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RVTEST_SIGBASE( x1,signature_x1_1)
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inst_0:
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// rd==x10, imm_val == 1020, imm_val > 0
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// opcode:c.addi4spn; dest:x10; immval:0x3fc
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TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3fc, 0x3fc, x1, 0, x2)
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inst_1:
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// rd==x13, imm_val == 508,
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// opcode:c.addi4spn; dest:x13; immval:0x1fc
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TEST_CADDI4SPN_OP( c.addi4spn, x13, 0x1fc, 0x1fc, x1, 4, x2)
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inst_2:
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// rd==x9, imm_val == 764,
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// opcode:c.addi4spn; dest:x9; immval:0x2fc
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TEST_CADDI4SPN_OP( c.addi4spn, x9, 0x2fc, 0x2fc, x1, 8, x2)
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inst_3:
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// rd==x8, imm_val == 892,
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// opcode:c.addi4spn; dest:x8; immval:0x37c
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TEST_CADDI4SPN_OP( c.addi4spn, x8, 0x37c, 0x37c, x1, 12, x2)
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inst_4:
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// rd==x14, imm_val == 956,
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// opcode:c.addi4spn; dest:x14; immval:0x3bc
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TEST_CADDI4SPN_OP( c.addi4spn, x14, 0x3bc, 0x3bc, x1, 16, x2)
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inst_5:
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// rd==x11, imm_val == 988,
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// opcode:c.addi4spn; dest:x11; immval:0x3dc
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TEST_CADDI4SPN_OP( c.addi4spn, x11, 0x3dc, 0x3dc, x1, 20, x2)
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inst_6:
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// rd==x15, imm_val == 1004,
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// opcode:c.addi4spn; dest:x15; immval:0x3ec
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TEST_CADDI4SPN_OP( c.addi4spn, x15, 0x3ec, 0x3ec, x1, 24, x2)
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inst_7:
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// rd==x12, imm_val == 1012,
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// opcode:c.addi4spn; dest:x12; immval:0x3f4
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TEST_CADDI4SPN_OP( c.addi4spn, x12, 0x3f4, 0x3f4, x1, 28, x2)
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inst_8:
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// imm_val == 1016,
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// opcode:c.addi4spn; dest:x10; immval:0x3f8
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TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3f8, 0x3f8, x1, 32, x2)
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inst_9:
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// imm_val == 512,
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// opcode:c.addi4spn; dest:x10; immval:0x200
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TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x200, 0x200, x1, 36, x2)
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inst_10:
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// imm_val == 256,
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// opcode:c.addi4spn; dest:x10; immval:0x100
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TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x100, 0x100, x1, 40, x2)
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inst_11:
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// imm_val == 128,
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// opcode:c.addi4spn; dest:x10; immval:0x80
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TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x80, 0x80, x1, 44, x2)
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inst_12:
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// imm_val == 4,
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// opcode:c.addi4spn; dest:x10; immval:0x4
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TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x4, 0x4, x1, 48, x2)
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inst_13:
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// imm_val == 680,
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// opcode:c.addi4spn; dest:x10; immval:0x2a8
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TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x2a8, 0x2a8, x1, 52, x2)
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inst_14:
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// imm_val == 340,
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// opcode:c.addi4spn; dest:x10; immval:0x154
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TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x154, 0x154, x1, 56, x2)
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inst_15:
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// imm_val == 64,
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// opcode:c.addi4spn; dest:x10; immval:0x40
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TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x40, 0x40, x1, 60, x2)
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inst_16:
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// imm_val == 32,
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// opcode:c.addi4spn; dest:x10; immval:0x20
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TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x20, 0x20, x1, 64, x2)
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inst_17:
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// imm_val == 16,
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// opcode:c.addi4spn; dest:x10; immval:0x10
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TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x10, 0x10, x1, 68, x2)
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inst_18:
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// imm_val == 8,
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// opcode:c.addi4spn; dest:x10; immval:0x8
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TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x8, 0x8, x1, 72, x2)
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#endif
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RVTEST_CODE_END
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RVMODEL_HALT
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RVTEST_DATA_BEGIN
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.align 4
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rvtest_data:
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.word 0xbabecafe
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RVTEST_DATA_END
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RVMODEL_DATA_BEGIN
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signature_x1_0:
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.fill 0*(XLEN/32),4,0xdeadbeef
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signature_x1_1:
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.fill 19*(XLEN/32),4,0xdeadbeef
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#ifdef rvtest_mtrap_routine
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mtrap_sigptr:
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.fill 64*(XLEN/32),4,0xdeadbeef
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#endif
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#ifdef rvtest_gpr_save
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gpr_save:
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.fill 32*(XLEN/32),4,0xdeadbeef
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#endif
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RVMODEL_DATA_END
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