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63f8a97939
cvw
/
wally-pipelined
History
Kip Macsai-Goren
da9ead2d95
Merge branch 'main' of
https://github.com/davidharrishmc/riscv-wally
into main
2021-07-23 15:16:01 -04:00
..
bin
config
fix UART RX FIFO bug where tail pointer can overtake head pointer
2021-07-22 02:09:41 -04:00
linux-testgen
fix UART RX FIFO bug where tail pointer can overtake head pointer
2021-07-22 02:09:41 -04:00
misc
ppa
regression
Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle.
2021-07-22 19:42:19 -05:00
src
Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's
2021-07-23 11:57:58 -05:00
testbench
Merge branch 'main' of
https://github.com/davidharrishmc/riscv-wally
into main
2021-07-23 15:16:01 -04:00
testgen
lint-wally
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