forked from Github_Repos/cvw
131 lines
4.6 KiB
Systemverilog
131 lines
4.6 KiB
Systemverilog
///////////////////////////////////////////
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// wallypipelinedhart.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Pipelined RISC-V Processor
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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/* verilator lint_on UNUSED */
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module wallypipelinedhart (
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input logic clk, reset,
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output logic [`XLEN-1:0] PCF,
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input logic [31:0] InstrF,
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// Privileged
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input logic TimerIntM, ExtIntM, SwIntM,
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input logic InstrAccessFaultF,
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input logic DataAccessFaultM,
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// Bus Interface
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input logic [`AHBW-1:0] HRDATA,
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input logic HREADY, HRESP,
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output logic HCLK, HRESETn,
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output logic [31:0] HADDR,
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output logic [`AHBW-1:0] HWDATA,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK,
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// Delayed signals for subword write
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output logic [2:0] HADDRD,
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output logic [3:0] HSIZED,
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output logic HWRITED
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);
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// logic [1:0] ForwardAE, ForwardBE;
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logic StallF, StallD, StallE, StallM, StallW;
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logic FlushD, FlushE, FlushM, FlushW;
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logic RetM, TrapM;
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// new signals that must connect through DP
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logic CSRWriteM, PrivilegedM;
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logic [`XLEN-1:0] SrcAM;
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// logic [31:0] InstrF;
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logic [31:0] InstrD, InstrM;
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logic [`XLEN-1:0] PCE, PCM, PCLinkW;
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logic [`XLEN-1:0] PCTargetE;
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logic [`XLEN-1:0] CSRReadValW;
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logic [`XLEN-1:0] PrivilegedNextPCM;
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logic [1:0] MemRWM;
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logic InstrValidW;
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logic InstrMisalignedFaultM;
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logic DataMisalignedM;
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logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
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logic LoadMisalignedFaultM, LoadAccessFaultM;
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logic StoreMisalignedFaultM, StoreAccessFaultM;
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logic [`XLEN-1:0] InstrMisalignedAdrM;
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logic [`XLEN-1:0] zero = 0;
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logic PCSrcE;
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logic CSRWritePendingDEM;
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logic LoadStallD;
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logic [4:0] SetFflagsM;
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logic [2:0] FRM_REGW;
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logic FloatRegWriteW;
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// bus interface to dmem
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logic MemReadM, MemWriteM;
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logic [2:0] Funct3M;
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logic [`XLEN-1:0] MemAdrM, MemPAdrM, WriteDataM;
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logic [`XLEN-1:0] ReadDataW;
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logic [`XLEN-1:0] InstrPAdrF;
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logic InstrReadF;
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logic DataStall, InstrStall;
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logic InstrAckD, MemAckW;
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ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache
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ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller
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dmem dmem(.*); // data cache unit
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/*
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ahblite ebu(
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//.InstrReadF(1'b0),
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.InstrRData(InstrF), // hook up InstrF later
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.MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]),
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.*);
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*/
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// changing from this to the line above breaks the program. auipc at 104 fails; seems to be flushed.
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// Would need to insertinstruction as InstrD, not InstrF
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ahblite ebu(
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.InstrReadF(1'b0),
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.InstrRData(), // hook up InstrF later
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.MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]),
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.*);
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/*
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mdu mdu(.*); // multiply and divide unit
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fpu fpu(.*); // floating point unit
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*/
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hazard hzu(.*); // global stall and flush control
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// Priveleged block operates in M and W stages, handling CSRs and exceptions
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privileged priv(.*);
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// add FPU here, with SetFflagsM, FRM_REGW
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// presently stub out SetFlagsM and FloatRegWriteW
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assign SetFflagsM = 0;
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assign FloatRegWriteW = 0;
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endmodule
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