forked from Github_Repos/cvw
364 lines
15 KiB
Systemverilog
364 lines
15 KiB
Systemverilog
///////////////////////////////////////////
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// icache.sv
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//
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// Written: jaallen@g.hmc.edu 2021-03-02
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// Modified:
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//
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// Purpose: Cache instructions for the ifu so it can access memory less often, saving cycles
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module icache(
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// Basic pipeline stuff
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input logic clk, reset,
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input logic StallF, StallD,
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input logic FlushD,
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// Upper bits of physical address for PC
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input logic [`XLEN-1:12] UpperPCPF,
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// Lower 12 bits of virtual PC address, since it's faster this way
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input logic [11:0] LowerPCF,
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// Data read in from the ebu unit
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input logic [`XLEN-1:0] InstrInF,
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input logic InstrAckF,
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// Read requested from the ebu unit
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output logic [`XLEN-1:0] InstrPAdrF,
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output logic InstrReadF,
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// High if the instruction currently in the fetch stage is compressed
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output logic CompressedF,
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// High if the icache is requesting a stall
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output logic ICacheStallF,
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// The raw (not decompressed) instruction that was requested
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// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
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output logic [31:0] InstrRawD
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);
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// Configuration parameters
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// TODO Move these to a config file
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localparam integer ICACHELINESIZE = 256;
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localparam integer ICACHENUMLINES = 512;
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// Input signals to cache memory
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logic FlushMem;
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logic [`XLEN-1:12] ICacheMemReadUpperPAdr;
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logic [11:0] ICacheMemReadLowerAdr;
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logic ICacheMemWriteEnable;
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logic [ICACHELINESIZE-1:0] ICacheMemWriteData;
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logic [`XLEN-1:0] ICacheMemWritePAdr;
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// Output signals from cache memory
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logic [`XLEN-1:0] ICacheMemReadData;
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logic ICacheMemReadValid;
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rodirectmappedmem #(.LINESIZE(ICACHELINESIZE), .NUMLINES(ICACHENUMLINES)) cachemem(
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.*,
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.flush(FlushMem),
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.ReadUpperPAdr(ICacheMemReadUpperPAdr),
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.ReadLowerAdr(ICacheMemReadLowerAdr),
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.WriteEnable(ICacheMemWriteEnable),
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.WriteLine(ICacheMemWriteData),
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.WritePAdr(ICacheMemWritePAdr),
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.DataWord(ICacheMemReadData),
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.DataValid(ICacheMemReadValid)
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);
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icachecontroller #(.LINESIZE(ICACHELINESIZE)) controller(.*);
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assign FlushMem = 1'b0;
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endmodule
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module icachecontroller #(parameter LINESIZE = 256) (
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// Inputs from pipeline
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input logic clk, reset,
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input logic StallF, StallD,
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input logic FlushD,
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// Input the address to read
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// The upper bits of the physical pc
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input logic [`XLEN-1:12] UpperPCPF,
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// The lower bits of the virtual pc
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input logic [11:0] LowerPCF,
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// Signals to/from cache memory
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// The read coming out of it
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input logic [`XLEN-1:0] ICacheMemReadData,
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input logic ICacheMemReadValid,
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// The address at which we want to search the cache memory
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output logic [`XLEN-1:12] ICacheMemReadUpperPAdr,
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output logic [11:0] ICacheMemReadLowerAdr,
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// Load data into the cache
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output logic ICacheMemWriteEnable,
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output logic [LINESIZE-1:0] ICacheMemWriteData,
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output logic [`XLEN-1:0] ICacheMemWritePAdr,
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// Outputs to rest of ifu
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// High if the instruction in the fetch stage is compressed
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output logic CompressedF,
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// The instruction that was requested
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// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
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output logic [31:0] InstrRawD,
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// Outputs to pipeline control stuff
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output logic ICacheStallF,
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// Signals to/from ahblite interface
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// A read containing the requested data
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input logic [`XLEN-1:0] InstrInF,
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input logic InstrAckF,
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// The read we request from main memory
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output logic [`XLEN-1:0] InstrPAdrF,
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output logic InstrReadF
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);
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// Happy path signals
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logic [31:0] AlignedInstrRawF, AlignedInstrRawD;
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logic FlushDLastCycleN;
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logic PCPMisalignedF;
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const logic [31:0] NOP = 32'h13;
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// Misaligned signals
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logic [`XLEN:0] MisalignedInstrRawF;
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logic MisalignedStall;
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// Cache fault signals
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logic FaultStall;
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// Detect if the instruction is compressed
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assign CompressedF = AlignedInstrRawF[1:0] != 2'b11;
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// Handle happy path (data in cache, reads aligned)
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generate
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if (`XLEN == 32) begin
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assign AlignedInstrRawF = LowerPCF[1] ? MisalignedInstrRawF : ICacheMemReadData;
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assign PCPMisalignedF = LowerPCF[1] && ~CompressedF;
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end else begin
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assign AlignedInstrRawF = LowerPCF[2]
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? (LowerPCF[1] ? MisalignedInstrRawF : ICacheMemReadData[63:32])
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: (LowerPCF[1] ? ICacheMemReadData[47:16] : ICacheMemReadData[31:0]);
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assign PCPMisalignedF = LowerPCF[2] && LowerPCF[1] && ~CompressedF;
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end
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endgenerate
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flopenr #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, AlignedInstrRawF, AlignedInstrRawD);
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flopr #(1) FlushDLastCycleFlop(clk, reset, ~FlushD & (FlushDLastCycleN | ~StallF), FlushDLastCycleN);
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mux2 #(32) InstrRawDMux(AlignedInstrRawD, NOP, ~FlushDLastCycleN, InstrRawD);
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// Stall for faults or misaligned reads
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always_comb begin
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assign ICacheStallF = FaultStall | MisalignedStall;
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end
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// Handle misaligned, noncompressed reads
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logic MisalignedState, NextMisalignedState;
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logic [15:0] MisalignedHalfInstrF;
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logic [15:0] UpperHalfWord;
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flopenr #(16) MisalignedHalfInstrFlop(clk, reset, ~FaultStall & (PCPMisalignedF & MisalignedState), AlignedInstrRawF[15:0], MisalignedHalfInstrF);
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flopenr #(1) MisalignedStateFlop(clk, reset, ~FaultStall, NextMisalignedState, MisalignedState);
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// When doing a misaligned read, swizzle the bits correctly
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generate
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if (`XLEN == 32) begin
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assign UpperHalfWord = ICacheMemReadData[31:16];
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end else begin
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assign UpperHalfWord = ICacheMemReadData[63:48];
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end
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endgenerate
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always_comb begin
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if (MisalignedState) begin
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assign MisalignedInstrRawF = {16'b0, UpperHalfWord};
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end else begin
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assign MisalignedInstrRawF = {ICacheMemReadData[15:0], MisalignedHalfInstrF};
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end
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end
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// Manage internal state and stall when necessary
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always_comb begin
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assign MisalignedStall = PCPMisalignedF & MisalignedState;
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assign NextMisalignedState = ~PCPMisalignedF | ~MisalignedState;
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end
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// Pick the correct address to read
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generate
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if (`XLEN == 32) begin
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assign ICacheMemReadLowerAdr = {LowerPCF[11:2] + (PCPMisalignedF & ~MisalignedState), 2'b00};
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end else begin
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assign ICacheMemReadLowerAdr = {LowerPCF[11:3] + (PCPMisalignedF & ~MisalignedState), 3'b00};
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end
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endgenerate
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assign ICacheMemReadUpperPAdr = UpperPCPF;
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// Handle cache faults
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localparam integer WORDSPERLINE = LINESIZE/`XLEN;
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localparam integer LOGWPL = $clog2(WORDSPERLINE);
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localparam integer OFFSETWIDTH = $clog2(LINESIZE/8);
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logic FetchState, EndFetchState, BeginFetchState;
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logic [LOGWPL:0] FetchWordNum, NextFetchWordNum;
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logic [`XLEN-1:0] LineAlignedPCPF;
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flopr #(1) FetchStateFlop(clk, reset, BeginFetchState | (FetchState & ~EndFetchState), FetchState);
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flopr #(LOGWPL+1) FetchWordNumFlop(clk, reset, NextFetchWordNum, FetchWordNum);
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genvar i;
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generate
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for (i=0; i < WORDSPERLINE; i++) begin
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flopenr #(`XLEN) flop(clk, reset, FetchState & (i == FetchWordNum), InstrInF, ICacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN]);
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end
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endgenerate
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// Enter the fetch state when we hit a cache fault
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always_comb begin
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assign BeginFetchState = ~ICacheMemReadValid & ~FetchState;
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end
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// Machinery to request the correct addresses from main memory
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always_comb begin
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assign InstrReadF = FetchState & ~EndFetchState;
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assign LineAlignedPCPF = {UpperPCPF, LowerPCF[11:OFFSETWIDTH], {OFFSETWIDTH{1'b0}}};
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assign InstrPAdrF = LineAlignedPCPF + FetchWordNum*(`XLEN/8);
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assign NextFetchWordNum = FetchState ? FetchWordNum+InstrAckF : {LOGWPL+1{1'b0}};
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end
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// Write to cache memory when we have the line here
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always_comb begin
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assign EndFetchState = FetchWordNum == {1'b1, {LOGWPL{1'b0}}} & FetchState;
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assign ICacheMemWritePAdr = LineAlignedPCPF;
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assign ICacheMemWriteEnable = EndFetchState;
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end
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// Stall the pipeline while loading a new line from memory
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always_comb begin
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assign FaultStall = FetchState | ~ICacheMemReadValid;
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end
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endmodule
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module oldicache(
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// Basic pipeline stuff
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input logic clk, reset,
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input logic StallF, StallD,
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input logic FlushD,
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// Upper bits of physical address for PC
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input logic [`XLEN-1:12] UpperPCPF,
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// Lower 12 bits of virtual PC address, since it's faster this way
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input logic [11:0] LowerPCF,
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// Data read in from the ebu unit
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input logic [`XLEN-1:0] InstrInF,
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// Read requested from the ebu unit
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output logic [`XLEN-1:0] InstrPAdrF,
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output logic InstrReadF,
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// High if the instruction currently in the fetch stage is compressed
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output logic CompressedF,
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// High if the icache is requesting a stall
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output logic ICacheStallF,
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// The raw (not decompressed) instruction that was requested
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// If the next instruction is compressed, the upper 16 bits may be anything
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output logic [31:0] InstrRawD
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);
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logic DelayF, DelaySideF, FlushDLastCyclen, DelayD;
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logic [1:0] InstrDMuxChoice;
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logic [15:0] MisalignedHalfInstrF, MisalignedHalfInstrD;
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logic [31:0] InstrF, AlignedInstrD;
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// Buffer the last read, for ease of accessing it again
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logic LastReadDataValidF;
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logic [`XLEN-1:0] LastReadDataF, LastReadAdrF, InDataF;
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// instruction for NOP
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logic [31:0] nop = 32'h00000013;
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// Temporary change to bridge the new interface to old behaviors
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logic [`XLEN-1:0] PCPF;
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assign PCPF = {UpperPCPF, LowerPCF};
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// This flop doesn't stall if StallF is high because we should output a nop
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// when FlushD happens, even if the pipeline is also stalled.
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flopr #(1) flushDLastCycleFlop(clk, reset, ~FlushD & (FlushDLastCyclen | ~StallF), FlushDLastCyclen);
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flopenr #(1) delayDFlop(clk, reset, ~StallF, DelayF & ~CompressedF, DelayD);
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flopenrc#(1) delayStateFlop(clk, reset, FlushD, ~StallF, DelayF & ~DelaySideF, DelaySideF);
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// This flop stores the first half of a misaligned instruction while waiting for the other half
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flopenr #(16) halfInstrFlop(clk, reset, DelayF & ~StallF, MisalignedHalfInstrF, MisalignedHalfInstrD);
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// This flop is here to simulate pulling data out of the cache, which is edge-triggered
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flopenr #(32) instrFlop(clk, reset, ~StallF, InstrF, AlignedInstrD);
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// These flops cache the previous read, to accelerate things
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flopenr #(`XLEN) lastReadDataFlop(clk, reset, InstrReadF & ~StallF, InstrInF, LastReadDataF);
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flopenr #(1) lastReadDataVFlop(clk, reset, InstrReadF & ~StallF, 1'b1, LastReadDataValidF);
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flopenr #(`XLEN) lastReadAdrFlop(clk, reset, InstrReadF & ~StallF, InstrPAdrF, LastReadAdrF);
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// Decide which address needs to be fetched and sent out over InstrPAdrF
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// If the requested address fits inside one read from memory, we fetch that
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// address, adjusted to the bit width. Otherwise, we request the lower word
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// and then the upper word, in that order.
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generate
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if (`XLEN == 32) begin
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assign InstrPAdrF = PCPF[1] ? ((DelaySideF & ~CompressedF) ? {PCPF[31:2], 2'b00} : {PCPF[31:2], 2'b00}) : PCPF;
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end else begin
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assign InstrPAdrF = PCPF[2] ? (PCPF[1] ? ((DelaySideF & ~CompressedF) ? {PCPF[63:3]+1, 3'b000} : {PCPF[63:3], 3'b000}) : {PCPF[63:3], 3'b000}) : {PCPF[63:3], 3'b000};
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end
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endgenerate
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// Read from memory if we don't have the address we want
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always_comb if (LastReadDataValidF & (InstrPAdrF == LastReadAdrF)) begin
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assign InstrReadF = 0;
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end else begin
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assign InstrReadF = 1;
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end
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// Pick from the memory input or from the previous read, as appropriate
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mux2 #(`XLEN) inDataMux(LastReadDataF, InstrInF, InstrReadF, InDataF);
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// If the instruction fits in one memory read, then we put the right bits
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// into InstrF. Otherwise, we activate DelayF to signal the rest of the
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// machinery to swizzle bits.
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generate
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if (`XLEN == 32) begin
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assign InstrF = PCPF[1] ? {16'b0, InDataF[31:16]} : InDataF;
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assign DelayF = PCPF[1];
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assign MisalignedHalfInstrF = InDataF[31:16];
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end else begin
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assign InstrF = PCPF[2] ? (PCPF[1] ? {16'b0, InDataF[63:48]} : InDataF[63:32]) : (PCPF[1] ? InDataF[47:16] : InDataF[31:0]);
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assign DelayF = PCPF[1] && PCPF[2];
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assign MisalignedHalfInstrF = InDataF[63:48];
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end
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endgenerate
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// We will likely need to stall later, but stalls are handled by the rest of the pipeline for now
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assign ICacheStallF = 0;
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// Detect if the instruction is compressed
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assign CompressedF = InstrF[1:0] != 2'b11;
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// Pick the correct output, depending on whether we have to assemble this
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// instruction from two reads or not.
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// Output the requested instruction (we don't need to worry if the read is
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// incomplete, since the pipeline stalls for us when it isn't), or a NOP for
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// the cycle when the first of two reads comes in.
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always_comb if (~FlushDLastCyclen) begin
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assign InstrDMuxChoice = 2'b10;
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end else if (DelayD & (MisalignedHalfInstrD[1:0] != 2'b11)) begin
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assign InstrDMuxChoice = 2'b11;
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end else begin
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assign InstrDMuxChoice = {1'b0, DelayD};
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end
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mux4 #(32) instrDMux (AlignedInstrD, {InstrInF[15:0], MisalignedHalfInstrD}, nop, {16'b0, MisalignedHalfInstrD}, InstrDMuxChoice, InstrRawD);
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endmodule
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