forked from Github_Repos/cvw
76 lines
2.9 KiB
Verilog
76 lines
2.9 KiB
Verilog
///////////////////////////////////////////
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// wally-pipelinedsoc.sv
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//
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// Written: David_Harris@hmc.edu 6 November 2020
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// Modified:
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//
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// Purpose: System on chip including pipelined processor and memories
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// Full RV32/64IC instruction set
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//
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// Note: the CSRs do not support the following features
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//- Disabling portions of the instruction set with bits of the MISA register
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//- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
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// As of January 2020, virtual memory is not yet supported
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module wallypipelinedsocwrapper (
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input clk, reset,
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// AHB Lite Interface
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// inputs from external memory
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input [`AHBW-1:0] HRDATAEXT,
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input HREADYEXT, HRESPEXT,
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output HSELEXT,
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// outputs to external memory, shared with uncore memory
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output HCLK, HRESETn,
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output [31:0] HADDR,
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output [`AHBW-1:0] HWDATA,
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output [`XLEN/8-1:0] HWSTRB,
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output HWRITE,
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output [2:0] HSIZE,
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output [2:0] HBURST,
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output [3:0] HPROT,
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output [1:0] HTRANS,
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output HMASTLOCK,
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output HREADY,
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// I/O Interface
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input TIMECLK,
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input [3:0] GPIOPinsIn_IO,
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output [4:0] GPIOPinsOut_IO,
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input UARTSin,
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output UARTSout,
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input ddr4_calib_complete,
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input [3:0] SDCDatIn,
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output SDCCLK,
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input SDCCmdIn,
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output SDCCmdOut,
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output SDCCmdOE
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);
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wire [31:0] GPIOPinsIn;
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wire [31:0] GPIOPinsOut;
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assign GPIOPinsOut_IO = GPIOPinsOut[4:0];
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assign GPIOPinsIn = {28'b0, GPIOPinsIn_IO};
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// wrapper for fpga
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wallypipelinedsoc wallypipelinedsoc(.*);
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endmodule
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